On Mon, Apr 15, 2019 at 10:33 PM Maxime Ripard <[email protected]> wrote: > > On Mon, Apr 15, 2019 at 04:22:22PM +0200, Ondřej Jirman wrote: > > DT would still probably need a re-work in the future, if the PRCM clock > > modeling the gate would be needed. > > Just reacting to that bit. > > I know we're pretty bad at this, and the documentation doesn't make it > any easier, but if you have any idea of how it should be modelled > next, then do that.
It seems to be just a clock gate, judging by previous (A80/A83T) SoCs. However since we lack documents for the PRCM, we might need to poke around to verify that it's actually there. Or maybe we could ask Allwinner very specific questions, like: - Does the PRCM have a gate controlling XO? - Is it bit 2 in register 0x44 in the PRCM? ChenYu > There's no reason to push it to a later time, it makes everyone's life > harder. > > Maxime > > -- > Maxime Ripard, Bootlin > Embedded Linux and Kernel engineering > https://bootlin.com > > -- > You received this message because you are subscribed to the Google Groups > "linux-sunxi" group. > To unsubscribe from this group and stop receiving emails from it, send an > email to [email protected]. > For more options, visit https://groups.google.com/d/optout. -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. For more options, visit https://groups.google.com/d/optout.
