On Mon, Jul 15, 2019 at 6:57 AM Andre Przywara <[email protected]> wrote: > > A tiny update, dropping "1333" from the LPDDR3 timings filename, because > it actually isn't 1333, as Icenowy pointed out correctly. Also adding > Jernej's review tags. For more details see the Changelog below. > ---------------- > > So far the SPL DRAM driver for the Allwinner H6 SoC only supports > LPDDR3 DRAM chips, which are used on most single board computers with > this SoC. > There are some TV boxes with the H6 out now, but most of them are > using DDR3 DRAM instead of LPDDR3. > > This series extends the existing H6 DRAM driver to cover DDR3 DRAMs > as well. The information used in these patches is from: > - register dumps after Allwinner's boot0 (libdram) has initialised > the DRAM > - some disassembly of the libdram library > - timing parameters as found in the boot0 binary > - comparison with Xilinx ZynqMP DRAM controller documentation > > The box I played with (Eachlink H6 Mini) has 3GB of DDR3-1600 chips and > runs at 840 MHz, however I couldn't get it to work with these parameters. > Instead Jernej suggested to use a lower clock and adjust some timing > parameters, which made it work for me as well. > > Many thanks to Jernej Skrabec for his help, also to others who helped > with testing and experiments. > > The first two patches contain some fixes for the existing driver. > Patch 3 moves the existing LPDDR3 timing parameters into a separate file, > patch 5 introduces the respective DDR3 timings, patch 6 adds some > generic delay lines values. > Patch 4 enhances the DRAM controller driver to program DDR3 specific > registers as well and use different settings on other registers. > The final patch introduces support for the Eachlink H6 Mini TV box, with > the usual device tree and defconfig file. > > Please have a look and comment! > > Cheers, > Andre. > > Changelog v2..v3: > - rebased against origin/master > - drop 1333 from LPDDR3 timings filename > - cosmetic change to comment > - adding Jernej's Reviewed-by: and Tested-by: tags > - updating defconfigs for two new boards > > Changelog v1..v2: > - name DDR2T mode bit > - explain bonding ID bit > - generalise message about non-supported DRAM types > - update comments about JEDEC values to match DDR3-1333 timings > - use recommended max(ns, cycles) timing formulas where appropriate > - add MAINTAINERS entry for the Eachlink H6 Mini box > > Andre Przywara (6): > sunxi: H6: DRAM: avoid memcpy() on MMIO registers > sunxi: H6: DRAM: follow recommended PHY init algorithm > sunxi: H6: move LPDDR3 timing definition into separate file > sunxi: H6: Add DDR3 support to DRAM controller driver > sunxi: H6: Add DDR3-1333 timings
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