On Fri, Nov 08, 2019 at 09:45:14AM +0100, Clément Péron wrote:
> From: Jernej Skrabec <[email protected]>
>
> PWM core has an option to bypass whole logic and output unchanged source
> clock as PWM output. This is achieved by enabling bypass bit.
>
> Note that when bypass is enabled, no other setting has any meaning, not
> even enable bit.
>
> This mode of operation is needed to achieve high enough frequency to
> serve as clock source for AC200 chip which is integrated into same
> package as H6 SoC.
>
> Signed-off-by: Jernej Skrabec <[email protected]>
> Signed-off-by: Clément Péron <[email protected]>
> ---
> drivers/pwm/pwm-sun4i.c | 44 +++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 44 insertions(+)
>
> diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
> index a10022d6c0fd..9cc928ab47bc 100644
> --- a/drivers/pwm/pwm-sun4i.c
> +++ b/drivers/pwm/pwm-sun4i.c
> @@ -3,6 +3,10 @@
> * Driver for Allwinner sun4i Pulse Width Modulation Controller
> *
> * Copyright (C) 2014 Alexandre Belloni
> <[email protected]>
> + *
> + * Limitations:
> + * - When outputing the source clock directly, the PWM logic will be bypassed
> + * and the currently running period is not guaranteed to be completed
> */
>
> #include <linux/bitops.h>
> @@ -73,6 +77,7 @@ static const u32 prescaler_table[] = {
>
> struct sun4i_pwm_data {
> bool has_prescaler_bypass;
> + bool has_direct_mod_clk_output;
> unsigned int npwm;
> };
>
> @@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip,
>
> val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
>
> + /*
> + * PWM chapter in H6 manual has a diagram which explains that if bypass
> + * bit is set, no other setting has any meaning. Even more, experiment
> + * proved that also enable bit is ignored in this case.
> + */
> + if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
> + sun4i_pwm->data->has_direct_mod_clk_output) {
> + state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
> + state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
I first thought you're losing precision here by reusing state->period
here, but with a divisor of 2 everything is fine.
> + state->polarity = PWM_POLARITY_NORMAL;
> + state->enabled = true;
> + return;
> + }
> +
> if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
> sun4i_pwm->data->has_prescaler_bypass)
> prescaler = 1;
> @@ -204,6 +223,7 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct
> pwm_device *pwm,
> struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
> struct pwm_state cstate;
> u32 ctrl;
> + bool bypass = false;
> int ret;
> unsigned int delay_us;
> unsigned long now;
> @@ -218,9 +238,24 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct
> pwm_device *pwm,
> }
> }
>
> + /*
> + * Although it would make much more sense to check for bypass in
> + * sun4i_pwm_calculate(), value of bypass bit also depends on "enabled".
I don't understand this reasoning. sun4i_pwm_calculate knows about
.enabled and also sun4i_pwm->data->has_direct_mod_clk_output. Maybe just
add a bool *bypass as parameter and move the logic there?
> + */
> + if (state->enabled) {
> + u32 clk_rate = clk_get_rate(sun4i_pwm->clk);
> + bypass = (state->period * clk_rate >= NSEC_PER_SEC) &&
> + (state->period * clk_rate < 2 * NSEC_PER_SEC) &&
> + (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC);
> + }
> +
This looks right now.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | https://www.pengutronix.de/ |
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