On Wed, Jan 6, 2021 at 10:33 PM Andre Przywara <[email protected]> wrote: > > The CEC clock on the H6 SoC is a bit special, since it uses a fixed > pre-dividier for one source clock (the PLL), but conveys the other clock > (32K OSC) directly. > We are using a fixed predivider array for that, but fail to use the right > flag to actually activate that. > > Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU") > Reported-by: Jernej Skrabec <[email protected]> > Signed-off-by: Andre Przywara <[email protected]>
Acked-by: Chen-Yu Tsai <[email protected]> -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/CAGb2v66G%2B4yUsCZmfuzbC4-8AbpQgtN%3DJt%3D4-7iXUTb%2BF429AQ%40mail.gmail.com.
