On Fri, 26 Feb 2021 00:13:23 +0800 Icenowy Zheng <icen...@aosc.io> wrote:
> This patchset contains two patches. > > The first one enables asymmetric dual rank DRAM on A64. This is needed > for 3GiB PinePhone, which has 2GiB rank 0 and 1GiB rank 1. This patch is > already used by the firmware flashed to PinePhone by factory. > > The second one enables dual rank (and asymmetric dual rank, although not > tested because of lack of real board) on R40. In order to support single > rank and dual rank at the same time, a new rank detection code is > implemented (because PIR_QSGATE-based one does not work on R40). The > code enables some error report facility of the DRAM controller, and > then tries to access rank 1 and then check for error. It's placed at 2nd > patch because it depends on the function that calculates rank 0 size > (and rank 1 base address) introduced in PATCH 1. Thanks, queued both for -next. I moved the call to mctl_r40_detect_rank_count() and mctl_set_cr() into sunxi_dram_init(), to avoid the size regression. Cheers, Andre > > Icenowy Zheng (2): > sunxi: support asymmetric dual rank DRAM on A64/R40 > sunxi: enable dual rank memory on R40 > > .../include/asm/arch-sunxi/dram_sunxi_dw.h | 11 +- > arch/arm/mach-sunxi/dram_sunxi_dw.c | 149 +++++++++++++++--- > 2 files changed, 131 insertions(+), 29 deletions(-) > -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20210331165740.724fbc3a%40slackpad.fritz.box.
