Update wiki page link to the Allwinner sunXi SoC Clock Control Module. Signed-off-by: Oleg Verych <ole...@gmail.com> --- Hi!
Can I ask additional question to those in the file? How is it possible to setup PLL7 to particular frequency and select it as a source to CSI0 via CCM_CSI0_CLK[1]? Is it possible to put such device tree example in documentation? Thanks! [1] https://linux-sunxi.org/Clock_Control_Module#CCM_CSI0_CLK Documentation/arm/sunxi/clocks.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/arm/sunxi/clocks.rst b/Documentation/arm/sunxi/clocks.rst index 23bd03f3e..f435bdd70 100644 --- a/Documentation/arm/sunxi/clocks.rst +++ b/Documentation/arm/sunxi/clocks.rst @@ -49,7 +49,7 @@ Q: Were can I learn more about the sunxi clocks? A: The linux-sunxi wiki contains a page documenting the clock registers, you can find it at - http://linux-sunxi.org/A10/CCM + https://linux-sunxi.org/Clock_Control_Module The authoritative source for information at this time is the ccmu driver released by Allwinner, you can find it at -- 2.20.1 -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/20230116232209.4744-1-olecom%40gmail.com.
