On Sun, Feb 05, 2023 at 09:50:22PM +0200, Oleg Verych wrote:
> Hello!
> 
> On 1/17/23, Oleg Verych <ole...@gmail.com> wrote:
> > Update wiki page link to the Allwinner sunXi SoC Clock Control Module.
> >
> > Signed-off-by: Oleg Verych <ole...@gmail.com>
> > ---
> > Hi!
> >
> > Can I ask additional question to those in the file?
> 
> Q:
> > How is it possible to setup PLL7 to particular frequency and select
> > it as a source to CSI0 via CCM_CSI0_CLK[1]?
> 
> A:
> by setting clock source and frequency via CCF[2] in a camera device as:
> 
> ```
>       ov5640: camera@3c {
>               compatible = "ovti,ov5640";
>               reg = <0x3c>;
>               pinctrl-names = "default";
>               pinctrl-0 = <&csi0_clk_pin>;
>               clocks = <&ccu CLK_CSI0>;
>               clock-names = "xclk";
> 
>               assigned-clocks = <&ccu CLK_CSI0>, <&ccu 17>; /* 17 = 
> CLK_PLL_VIDEO1 * /

You don't need the second clock.

>               assigned-clock-rates = <32000000>;
>               assigned-clock-parents = <&ccu 17>;
> ...
>               port {
>                       ov5640_to_csi0: endpoint {
> ...
> 
> ```
> [2] 
> https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml

I'm not sure why you're trying to do that in the first place, but please
note that this isn't a guarantee in any way. It could change at any
point in time after probe has been called.

> Set of other related questions:
> 
> Q: When trying to setup main CSI0 clock to 32MHz from example above,
> it is not possible to get integer mode value:
> 
> sun4i_csi_probe mclk: 31578948 Hz
> 
> Why it is so, while PLL7 can be configured to (3*(9 + 23)) = 96 MHz
> which then can be divided by (2 + 1) using CCM_CSI0_CLK [1] /
> CSI0_CLK_REG [A20_User_Manual_v1.4_20150510.pdf p.84]?

I think what happens with your DT bits is that CLK_CSI0 and PLL_VIDEO1
will be set to 32MHz, in that order.

> Q: Initial value for CSI0 ISP clock is not as hardcoded in
> `sun4i_csi_runtime_resume()`. Is it correct to hardcode the value for
> resume? E.g.[3]:
> ```
>       clk_prepare_enable(csi->ram_clk);
> >>    clk_set_rate(csi->isp_clk, 80000000);
>       clk_prepare_enable(csi->isp_clk);
> ```
> [3] 
> https://elixir.bootlin.com/linux/v6.1/source/drivers/media/platform/sunxi/sun4i-csi/sun4i_csi.c#L303

I guess? What's wrong with it?

> Q: Is there a good guide / how-to somewhere on how to suspend/resume
> A20-processor based devices, e.g. for `sun4i_csi_runtime_resume()`
> testing?

runtime PM is not related to suspend/resume. It will start and stop the
device whenever it's actually used instead of keeping it on all the
time.

If you start a capture and it works, then you've tested runtime PM

Maxime

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