Matthew Trescott writes: > Hi Dave, > > I made a bit of a mistake; I did not realize there is a new clocks binding > already mainline: > https://lore.kernel.org/netdev/20230605154010.49611-2-detlev.casan...@collabora.com/T/#u > > That patch puts the clock under control of the PHY driver, so in theory it > should have worked without Andre's patch at all, as long as the clock was a > property of the PHY node. It seems only the Realtek driver handles it for > now, > but that wouldn't be a problem in your case.
Sorry for the delay, I'm just getting back to this. Yes, that patch does solve the issue of using ephy-25m output for a crystal-less PHY solution. Note that patch is only for a few specific models of PHY. I had to expand it to work with others, but solution is the same. As mentioned before, the DI/T113 EMAC does require the PHY to feed it's 50mhz clock back into the SOC for it to complete soft reset, but the wait/timeout is already in the driver for this. It's unfortunate that there is an external dependency on this in the hardware design, but it is what it is. Thanks. -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscr...@googlegroups.com. To view this discussion on the web, visit https://groups.google.com/d/msgid/linux-sunxi/25984.34753.559715.896776%40gargle.gargle.HOWL.
