On Mon, 29 Apr 2002, Andrea Mazzoleni wrote:
> The PLL N divider is sometimes computed incorrectly.
>
> For example with this modeline :
> 21.2784 416 424 488 520 312 318 320 341 -hsync -vsync doublescan
>
> the values computed by the NV3ClockSelect function are :
> m=13 n=309 p=4
> There N is out of the 8 bit allowed range.
Thanks. I fixed the problem by using the newer clock calculation routine
from nv driver in XFree86. It actually also had this problem, but only
for high clock frequencies (>246MHz).
--
Matan Ziv-Av. [EMAIL PROTECTED]
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