Hi Rolandas, hello all, > I'll start to write a skeleton driver now. I'll send you code when I > think that there is something you should test. Depending on how much > time I'm able to spare for ftape it might take a month until your tape > drive is supported. Maybe faster. Following up to myself. Crazy me. Well, just FYI: I haven't written a driver yet, but I think I have assembled enough information to start coding. Now it depends on the how much time I'm able to spare for ftape :-o Just a few minutes ago I found out that the TST3200 uses the polynomial p(x) = x^16 + x^12 + x^5 + 1 to generate the CRC which is used to guarantee the integrity of the data transferred to and from the tape drive. The algorithm is the same which is used by the BackPack interface already supported by ftape, i.e. the least significant bit of each data byte is interpreted as the coefficient of the most significant power of x (the other way round seems more natural to me, but this is just a matter of taste). Actually, p(x) is not irreducible, but p(x) = (x+1)*(x^15+x^14+x^13+x^12+x^4+x^3+x^2+x+1) (over GF(2)) The register layout of the TST3200 is as follows: FDC registers are located at 0xc0. The control registers are located starting at 0x80. #define FT_FTSG_REG_CRC 0x80 /* CRC checksum */ #define FT_FTSG_REG_0x81 0x81 /* interrupt control ??? */ #define FT_FTSG_REG_0x82 0x82 /* needed for protocol selection ??? */ #define FT_FTSG_REG_MODE 0x83 /* transfer mode (r/w, ECC) */ #define FT_FTSG_REG_STATUS 0x84 /* status register */ #define FT_FTSG_REG_SEGWR 0x85 /* segment descriptor for writing */ #define FT_FTSG_REG_ADRWR 0x86 /* memory address for writing */ #define FT_FTSG_REG_0x87 0x87 #define FT_FTSG_REG_MEM 0x88 /* access memory */ #define FT_FTSG_REG_SEGRD 0x89 /* segment descriptor for reading */ #define FT_FTSG_REG_ADRRD 0x8a /* memory address for reading */ #define FT_FTSG_REG_DMACNT 0x8b /* memory count for DMA transfers */ #define FT_FTSG_REG_SEGDMA 0x8c /* segment descriptor for DMA transfers ? */ #define FT_FTSG_REG_0x8d 0x8d The TST3200 has 128k of builtin RAM. Its RAM is devided into 4 segments of 32k. Memory addresses are coded as a "segment descriptor" which runs from 0 to 3, and an offset into that 32k segment. There are different segment descriptors and offset registers for reading, writing and DMA transfer, but I still have to determine which of the registers is needed to initiate the DMA transfer starting at an offset, i.e. to retry reading some sectors after an error. Probably this is 0x8a. The TST3200 has a builtin ECC coprocessor, therefor only 29k need to be transferred from and to the tape drive. The status of the ECC error check can be determined by reading the status register 0x84. The ECC coprocessor is used if bit 3 (i.e. 0x08) is written to the "mode" register 0x83. Bit 0 (i.e. 0x01) signals that data is to be read, absence of bit 0 signals that data will be written. Bit 2 seems to be always set during real memory transfers. Don't know what it is. The interrupt status can be determined throught he status register. I still have to determine how interrupts are handled properly, but this is just a matter of writing another awk script to determine when the interrupt enable bit is set in the parport control register. Maybe the TST3200 uses just another "version" of the BackPack interface. Who knows. I have written to the support team at Seagate. Maybe they can shine some light on it. In case the write an answer at all. Has somebody else on this list a parport Seagate Tapestore 3200 AND a parallel port which is capable of EPP mode? Rolandas system only has an SPP parallel port, so I only can hack a driver which supports SPP at the moment. Yours Claus -- Claus-Justus Heine [EMAIL PROTECTED] http://www.math1.rwth-aachen.de/~heine/ Ftape - the Linux Floppy Tape Project Home Page : http://www.math1.rwth-aachen.de/~heine/ftape/ CVS Repos. : http://iris3.math1.rwth-aachen.de:8000/cvsweb/ Bug Reports : http://iris3.math1.rwth-aachen.de:8080/gnats/ [EMAIL PROTECTED] Mailing-list: [EMAIL PROTECTED]
