On Tue, Jun 7, 2011 at 6:53 PM, Robert Morell <[email protected]> wrote:
> Although disp1 and disp2 have 7.1 divisors, their corresponding
> registers in the clk_rst block are not the interface to program the
> divisors.  Setting the generic DIV_U71 flag may cause the code to
> attempt to program the clock at a different divisor, which will confuse
> any code attempting to use that clock since it isn't actually being
> divided.
>
> Signed-off-by: Robert Morell <[email protected]>
> ---
>
> This bugfix applies to Linus's 2.6.39.  However, since no drivers are using
> these clocks in that kernel, this should probably just be queued up for 3.0.
>
> It also applies to linux-tegra-2.6.3[69].
>
> Thanks.
>
>  arch/arm/mach-tegra/tegra2_clocks.c |    4 ++--
>  1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-tegra/tegra2_clocks.c 
> b/arch/arm/mach-tegra/tegra2_clocks.c
> index bb61807..0fe9b3e 100644
> --- a/arch/arm/mach-tegra/tegra2_clocks.c
> +++ b/arch/arm/mach-tegra/tegra2_clocks.c
> @@ -2182,8 +2182,8 @@ struct clk tegra_list_clks[] = {
>        PERIPH_CLK("tvo",       "tvo",                  NULL,   49,     0x188, 
>  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min 
> voltage */
>        PERIPH_CLK("hdmi",      "hdmi",                 NULL,   51,     0x18c, 
>  600000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min 
> voltage */
>        PERIPH_CLK("tvdac",     "tvdac",                NULL,   53,     0x194, 
>  250000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* requires min 
> voltage */
> -       PERIPH_CLK("disp1",     "tegradc.0",            NULL,   27,     
> 0x138,  600000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* scales 
> with voltage and process_id */
> -       PERIPH_CLK("disp2",     "tegradc.1",            NULL,   26,     
> 0x13c,  600000000, mux_pllp_plld_pllc_clkm,     MUX | DIV_U71), /* scales 
> with voltage and process_id */
> +       PERIPH_CLK("disp1",     "tegradc.0",            NULL,   27,     
> 0x138,  600000000, mux_pllp_plld_pllc_clkm,     MUX), /* scales with voltage 
> and process_id */
> +       PERIPH_CLK("disp2",     "tegradc.1",            NULL,   26,     
> 0x13c,  600000000, mux_pllp_plld_pllc_clkm,     MUX), /* scales with voltage 
> and process_id */
>        PERIPH_CLK("usbd",      "fsl-tegra-udc",        NULL,   22,     0,     
>  480000000, mux_clk_m,                   0), /* requires min voltage */
>        PERIPH_CLK("usb2",      "tegra-ehci.1",         NULL,   58,     0,     
>  480000000, mux_clk_m,                   0), /* requires min voltage */
>        PERIPH_CLK("usb3",      "tegra-ehci.2",         NULL,   59,     0,     
>  480000000, mux_clk_m,                   0), /* requires min voltage */
> --
> 1.7.3.4
>
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Ack, putting in for-next for 3.1
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