On 11/12/2012 10:03 PM, Laxman Dewangan wrote: > Add OF_DEV_AUXDATA for sflash controller driver for Tegra20 > board dt files. > Set the parent clock of sflash controller to PLLP and configure > clock to 20MHz.
Thanks, applied to Tegra's for-3.8/soc branch. -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
