> Yes, the above are correct. The way we wrote the driver is that to > support the sync and async both. > When driver configures spi controller and ready for receive data then > the callback from client is called. This callback is registered through > spi_tegra_register_callback(). The client code then can inform master in > this callback to start transfer through some mechanism i.e. gpio.
One more question. >From the Tegra 2 Manual, SPI slave section, I read (I cannot copy it because of DRM and Nvidia legal stuff) that the clock signal *must* has 1 cycle delay between each word (or packet in packet mode); but I don't read from the master section that the master controller provide 1 cycle delay between each word (or packet). If I connect a Tegra 2 SPI Master with a Tegra 2 SPI slave .... it works? Thank you -- Federico Vaga -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
