On 12/20/2012 01:10 PM, Lucas Stach wrote:
> Am Donnerstag, den 20.12.2012, 12:44 -0700 schrieb Stephen Warren:
>> On 12/19/2012 04:17 PM, Lucas Stach wrote:
>>> This adds the driver for the Tegra 2x AC97 host controller.
>>> +static void tegra20_ac97_codec_warm_reset(struct snd_ac97 *ac97)
>>> +{
>>> + u32 readback;
>>> + unsigned long timeout;
>>> +
>>> + /*
>>> + * although sync line is driven by the DAC pad group warm reset using
>>> + * the controller cmd is not working, have to toggle sync line
>>> + * manually.
>>> + */
>>> + gpio_request(workdata->sync_gpio, "codec-sync");
>>
>> Hmm. There's an AC'97 command to reset the CODEC and we don't implement
>> it? Uggh.
>
> As far as I could figure from the downstream register doc there is a
> command implemented in the host controller that's supposed to do the
> warm reset, but in my testing it didn't work. Sadly I have not received
> any documentation about the host controller from NVIDIA up until now, so
> I don't now if we could make this work somehow. Bug Submission ID#:
> 196075
What system was that bug submitted into? It's not a regular NVIDIA
internal bug number. I'll see who I can ask about this feature...
>>> + ac97->sync_gpio = of_get_named_gpio(pdev->dev.of_node,
>>> + "nvidia,codec-sync-gpio", 0);
>>> + if (!gpio_is_valid(ac97->sync_gpio)) {
>>> + dev_err(&pdev->dev, "no codec-sync GPIO supplied\n");
>>> + goto err_clk_put;
>>> + }
>>
>> I don't know what this is, so I'll ask if it's strictly required too.
>
> Until we manage to get the host controller warm reset command working
> this is fixed to be the _FS line of the DAP connected to the codec, so
> strictly required.
I'd like to investigate whether the warm reset command can be made to
work before actually committing to a DT binding that requires this GPIO
to be specified; the DT binding is supposed to be basically static.
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