On Thu, Mar 14, 2013 at 04:27:05PM +0100, Thierry Reding wrote: > Under some circumstances the PLLE needs to be retrained, in which case > access to the PMC registers is required. Fix this by passing a pointer > to the PMC registers instead of NULL when registering the PLLE clock. > > Signed-off-by: Thierry Reding <[email protected]>
Acked-By: Peter De Schrijver <[email protected]> > --- > drivers/clk/tegra/clk-tegra20.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c > index b92d48b..bf19400 100644 > --- a/drivers/clk/tegra/clk-tegra20.c > +++ b/drivers/clk/tegra/clk-tegra20.c > @@ -703,7 +703,7 @@ static void tegra20_pll_init(void) > clks[pll_a_out0] = clk; > > /* PLLE */ > - clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, NULL, > + clk = tegra_clk_register_plle("pll_e", "pll_ref", clk_base, pmc_base, > 0, 100000000, &pll_e_params, > 0, pll_e_freq_table, NULL); > clk_register_clkdev(clk, "pll_e", NULL); Cheers, Peter. -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
