On 06/07/2013 06:19 AM, Paul Walmsley wrote:
> Add the input clocks needed by the DFLL IP blocks. Initialize them to
> 51MHz (as required by the DFLL GFD) and to use the PLL_P clock source.
>
> This patch is a collaboration with Peter De Schrijver
> <[email protected]>.
>
> Thanks to Laxman Dewangan <[email protected]> for identifying the
> requirement to keep the DFLL clocks enabled to resolve PWR_I2C timeout
> issues.
> diff --git a/drivers/clk/tegra/clk-tegra114.c
> b/drivers/clk/tegra/clk-tegra114.c
> @@ -792,6 +794,7 @@ enum tegra114_clk {
> audio1, audio2, audio3, audio4, spdif, clk_out_1, clk_out_2, clk_out_3,
> blink, xusb_host_src = 252, xusb_falcon_src, xusb_fs_src, xusb_ss_src,
> xusb_dev_src, xusb_dev, xusb_hs_src, sclk, hclk, pclk, cclk_g, cclk_lp,
> + dfll_ref = 264, dfll_soc,
Those values need to be added to the DT binding documentation, or rather
the header file that now defines the constants for that binding.
BTW, I was rather hoping that Hiroshi would have converted the clock
drivers to actually use that header file by now... Then this requirement
would have been a lot more obvious. Hiroshi, are patches for that coming
soon? Paul, if not, are you able to do that?
For reference, include/dt-bindings/clock/tegra*-car.h.
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