On 10/29/2013 08:40 AM, Thierry Reding wrote: > Signed-off-by: Thierry Reding <[email protected]>
What does this patch solve? A description would be nice. I thought that this PLL essentially was fixed; while it may have some registers than /can/ change the rate, hasn't the HW team only characterized it to run at the single frequency that PCIe requires, hence SW is supposed to treat it as fixed? -- To unsubscribe from this list: send the line "unsubscribe linux-tegra" in the body of a message to [email protected] More majordomo info at http://vger.kernel.org/majordomo-info.html
