On Wed, Apr 11, 2001 at 11:28:33PM +0200, Martin Diehl wrote:
<...>
> My concern on alignment is based on:
>
> PCI is 32 bit wide (at least) and BM-DMA is probably done using
> burst-cycles, i.e. 32 bit transfered for every PCI clock and _no_ address
> line incrementing by the BM-device (the BM-target has to manage this by
> itself during burst cycles). So I don't see a way to execute a burst
> transfer with len != n*4 (byte). Well, I can not exclude there is
<...>
Who says that all transfers are done with burst accesses? Every PCI-master
that allows single byte transfers (and UHCI and OHCI are among them)
automatically split accesses in an unaligned/non-burst access, then the
burts part and then the rest as an unaligned access.
The restriction for UHCI is that the lower 2 bits of the memory address in
the TD are used for other purposes, so UHCI transfers can't start at non
4-byte-aligned addresses, but that has nothing to do with PCI itself.
The main problem with the data memory is simply that some locations are not
guaranteed to map continuosly to PCI space, so that accidently crossing a
page boundary may fail. Some time ago, Alan Cox explained that the kernel stack
currently is continous, but may not longer continous in the future.
--
Georg Acher, [EMAIL PROTECTED]
http://www.in.tum.de/~acher/
"Oh no, not again !" The bowl of petunias
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