On Thu, 19 Apr 2001, Pete Zaitcev wrote:
> > > > *buffer = 0x12345f00;
> > > > dma_addr = pci_map_single(dev,buffer,len,PCI_DMA_TODEVICE);
> > > > pci_write_config_dword(dev,reg,dma_addr);
> > > >
> > > > If caching is write-back my feeling is there is nothing that guarantees
> > > > the modification went to physmem before the device starts reading from it.
> > >
> > > Exactly. That's why you must call pci_dma_sync_single before the
> > > transfer, if you used pci_map_single.
> >
> > I didn't see that in DMA-mapping.txt ... if it's needed, I'd expect
> > that pci_map_single would do that. The sync_single call is mentioned
> > in the context of reusing mappings.
>
> David is absolutely right for the code snippet above,
> e.g. if accesses happen _before_ the map, no sync is needed.
Yes, for sure. Apparently my description that followed the snippet above
in the original posting wasn't clear enough.
I believe we all agree, that giving a dma_addr_t handle to the device
requires cpu cache synchronisation have been achieved beforehand (in the
case of streaming mapping). We also agree that - according to
DMA-mapping.txt - this should be handled by pci_map_single() when creating
the mapping and by pci_dma_sync_single() in the middle of a existing
streaming mapping.
My point however is, I'm not sure whether the implementation of this API
for x86 really provides what is said in DMA-mapping.txt: I don't see any
cache synchronisation in the path of neither pci_map_single() nor
pci_dma_sync_single(). Please have a look at include/asm-i386/pci.h
Unless I missed something obvious, for x86 it all comes down to
pci_map_single(...,kvaddr,...) == __pa(kvaddr)
and
pci_dma_sync_single(...) == nothing!
Due to the rather simple address spaces for x86 this is correct as far as
address mapping and visibility is concerned - for x86 we have
virt_to_bus() == virt_to_phys() == __pa().
However, there seems to be no cache synchronisation. Similar point for
consistent mappings which are basically a combination of
__get_free_pages() and __pa() for x86 in arch/i386/kernel/pci-dma.c
So my question was directed to what I've probably missed that ensures
cache synchronisation for DMA-mappings on x86.
Martin
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