# This is a BitKeeper generated patch for the following project:
# Project Name: Linux kernel tree
# This patch format is intended for GNU patch command version 2.5 or higher.
# This patch includes the following deltas:
# ChangeSet 1.543 -> 1.544
# drivers/usb/hcd/ehci-q.c 1.7 -> 1.8
# drivers/usb/hcd/ehci-hub.c 1.5 -> 1.6
# drivers/usb/hcd/ehci-hcd.c 1.8 -> 1.9
#
# The following is the BitKeeper ChangeSet Log
# --------------------------------------------
# 02/03/18 [EMAIL PROTECTED] 1.544
# USB echi and Intel ICH
#
# This updates the Philips tweak so that it also applies
# to late-model ICH chips from Intel. (Or so I'm told ... :)
# That's at least three EHCI implementations known to
# behave on Linux. (And one hopes VIA soon too...)
#
# It also cleans up a few comments relating to 64bit DMA;
# recent API spec updates make it look like no games are
# needed with the PCI DMA mask -- it doesn't change the
# segment used by pci_pool allocations, so it just needs
# to get turned on if the overall system does 64bit DMA.
#
# I've a query in to see if those Philips/Intel tweaks are
# chip quirks, or just something the EHCI 1.0 spec isn't
# at all clear about.
# --------------------------------------------
#
diff -Nru a/drivers/usb/hcd/ehci-hcd.c b/drivers/usb/hcd/ehci-hcd.c
--- a/drivers/usb/hcd/ehci-hcd.c Wed Apr 3 16:40:11 2002
+++ b/drivers/usb/hcd/ehci-hcd.c Wed Apr 3 16:40:11 2002
@@ -208,6 +208,7 @@
/* controller state: unknown --> reset */
/* EHCI spec section 4.1 */
+ // FIXME require STS_HALT before reset...
ehci_reset (ehci);
writel (INTR_MASK, &ehci->regs->intr_enable);
writel (ehci->periodic_dma, &ehci->regs->frame_list);
@@ -215,16 +216,17 @@
/*
* hcc_params controls whether ehci->regs->segment must (!!!)
* be used; it constrains QH/ITD/SITD and QTD locations.
- * By default, pci_alloc_consistent() won't hand out addresses
- * above 4GB (via pdev->dma_mask) so we know this value.
- *
- * NOTE: that pdev->dma_mask setting means that all DMA mappings
- * for I/O buffers will have the same restriction, though it's
- * neither necessary nor desirable in that case.
+ * pci_pool consistent memory always uses segment zero.
*/
if (HCC_64BIT_ADDR (hcc_params)) {
writel (0, &ehci->regs->segment);
- info ("using segment 0 for 64bit DMA addresses ...");
+ /*
+ * FIXME Enlarge pci_set_dma_mask() when possible. The DMA
+ * mapping API spec now says that'll affect only single shot
+ * mappings, and the pci_pool data will stay safe in seg 0.
+ * That's what we want: no extra copies for USB transfers.
+ */
+ info ("restricting 64bit DMA mappings to segment 0 ...");
}
/* clear interrupt enables, set irq latency */
@@ -234,6 +236,9 @@
temp |= 1 << (16 + log2_irq_thresh);
// keeping default periodic framelist size
temp &= ~(CMD_IAAD | CMD_ASE | CMD_PSE),
+ // Philips, Intel, and maybe others need CMD_RUN before the
+ // root hub will detect new devices (why?); NEC doesn't
+ temp |= CMD_RUN;
writel (temp, &ehci->regs->command);
dbg_cmd (ehci, "init", temp);
@@ -260,7 +265,7 @@
readl (&ehci->regs->command); /* unblock posted write */
/* PCI Serial Bus Release Number is at 0x60 offset */
- pci_read_config_byte(hcd->pdev, 0x60, &tempbyte);
+ pci_read_config_byte (hcd->pdev, 0x60, &tempbyte);
temp = readw (&ehci->caps->hci_version);
info ("USB %x.%x support enabled, EHCI rev %x.%2x",
((tempbyte & 0xf0)>>4),
@@ -387,6 +392,8 @@
// restore pci FLADJ value
// khubd and drivers will set HC running, if needed;
hcd->state = USB_STATE_READY;
+ // FIXME Philips/Intel/... etc don't really have a "READY"
+ // state ... turn on CMD_RUN too
for (i = 0; i < ports; i++) {
int temp = readl (&ehci->regs->port_status [i]);
diff -Nru a/drivers/usb/hcd/ehci-hub.c b/drivers/usb/hcd/ehci-hub.c
--- a/drivers/usb/hcd/ehci-hub.c Wed Apr 3 16:40:11 2002
+++ b/drivers/usb/hcd/ehci-hub.c Wed Apr 3 16:40:11 2002
@@ -309,13 +309,6 @@
hcd->bus_name, wIndex + 1);
temp |= PORT_OWNER;
} else {
- /* Philips 1562 wants CMD_RUN to reset */
- if (!HCD_IS_RUNNING(ehci->hcd.state)) {
- u32 cmd = readl (&ehci->regs->command);
- cmd |= CMD_RUN;
- writel (cmd, &ehci->regs->command);
- ehci->hcd.state = USB_STATE_RUNNING;
- }
vdbg ("%s port %d reset",
hcd->bus_name, wIndex + 1);
temp |= PORT_RESET;
diff -Nru a/drivers/usb/hcd/ehci-q.c b/drivers/usb/hcd/ehci-q.c
--- a/drivers/usb/hcd/ehci-q.c Wed Apr 3 16:40:11 2002
+++ b/drivers/usb/hcd/ehci-q.c Wed Apr 3 16:40:11 2002
@@ -436,14 +436,6 @@
if (usb_pipecontrol (urb->pipe)) {
/* control request data is passed in the "setup" pid */
-
- /* NOTE: this isn't smart about 64bit DMA, since it uses the
- * default (32bit) mask rather than using the whole address
- * space. we could set pdev->dma_mask to all-ones while
- * getting this mapping, locking it and restoring before
- * allocating qtd/qh/... or maybe only do that for the main
- * data phase (below).
- */
qtd->buf_dma = pci_map_single (
ehci->hcd.pdev,
urb->setup_packet,
@@ -472,7 +464,6 @@
*/
len = urb->transfer_buffer_length;
if (likely (len > 0)) {
- /* NOTE: sub-optimal mapping with 64bit DMA (see above) */
buf = map_buf = pci_map_single (ehci->hcd.pdev,
urb->transfer_buffer, len,
usb_pipein (urb->pipe)
_______________________________________________
[EMAIL PROTECTED]
To unsubscribe, use the last form field at:
https://lists.sourceforge.net/lists/listinfo/linux-usb-devel
