On Thu, May 09, 2002, David Brownell <[EMAIL PROTECTED]> wrote: > (Linus said ...) > > > SMP-atomicity automatically gives DMA master atomicity on x86 too, but it > > is certainly the case that that is not guaranteed on other architectures > > Similarly, not all devices use read/modify/write ... > when they know they "own" the data, and have the > previous value cached, it's just "write". It's more > complex (expensive) and error prone to have the > read/modify/write logic.
I just checked the UHCI spec and the only verbage it uses is "update" which isn't specific enough to say what it does. So, I'm thinking that te atomic bit update route is a bad idea now. In the shower I thought of a different way which will be safe and hopefully will preserve some performance. When we want to deactivate FSBR on an URB's transfer, we can switch it from breadth first to depth first. But only do like every 5 or 10 (or some number) TD's to make sure it doesn't eat up all of the bandwidth. I think I'll implement that this weekend. JE _______________________________________________________________ Have big pipes? SourceForge.net is looking for download mirrors. We supply the hardware. You get the recognition. Email Us: [EMAIL PROTECTED] _______________________________________________ [EMAIL PROTECTED] To unsubscribe, use the last form field at: https://lists.sourceforge.net/lists/listinfo/linux-usb-devel
