> The real race is in uhci_fsbr_timeout. If the transfer starts moving
> again, then we will have read td->status, set the IOC bit and wrote it
> back out again while the HC clears the ACTIVE bit behind our backs.
And by using read/modify/write, you ensure that you won't lose
that bit. Even if the HC just overwrites td->status from a copy
which it previously cached. That deserves comments in source.
A 32bit atomic swap could do the same; I remember it as a more
classic portable SMP primitive than any bit operations (or even than
atomic increment/decrement). Yet I don't see it in <asm/*.h> ... hmm.
- Dave
p.s. Seems like only uhci_fsbr_timeout() has any reason not
to use standard C bitops for setting/clearing bits, since all
other cases operate on inactive TDs, or deal with requests
for interrupts (which might come in anyway).
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