On Thu, 2 Oct 2003, Richard Stover wrote: > What do you think determines this current limit of 3 transactions > per microframe? Is it primarily cpu speed that sets the amount > of time it takes to get another transaction going? I suspect it > is not the FX2 chip, but I haven't verified that yet.
It's not easy to say. In fact, without monitoring the bus you can't really be sure that 3 transactions per microframe is the limiting transfer rate; it may just be an average and there may be bursts that go higher. Perhaps the FX2 chip is the bottleneck, perhaps the bandwidth between the host controller and system memory. Again, without monitoring the bus it's impossible to tell. However, if your transfer buffers are large (tens of kbytes) then the operating system will _not_ be the bottleneck. And remember, although bulk transfers aren't guaranteed any bandwidth at all, if nothing else is using the bus they will receive nearly 100% of the bandwidth. That's a lot more than the amount guaranteed for interrupt transfers. Alan Stern ------------------------------------------------------- This sf.net email is sponsored by:ThinkGeek Welcome to geek heaven. http://thinkgeek.com/sf _______________________________________________ [EMAIL PROTECTED] To unsubscribe, use the last form field at: https://lists.sourceforge.net/lists/listinfo/linux-usb-devel
