However, it appears that the MIPs processor does 32 bit bus writes,
> which means that the frame_no and pad1 fields are swapped when > written to the fpga/usb controller.
That is, this MIPS processor (all of them?) doesn't implement 8 or 16 bit bus accesses.
As I recall, some early RISC hardware thought that saving such addressing logic was a big win; though the evidence today seems to be against that and several other RISC mantras.
> The correct way for Intel to have done this, in my opinion, is > to define all hardware descriptor elements as u32...
Actually Intel had nothing to do with OHCI; see the copyright statements on the front page of the spec. Intel did UHCI, which had licensing problems (at least at first) and wasn't particularly OS-friendly; so other vendors (Compaq, Microsoft, and NatSemi) did an "Open" HC Interface.
And likewise Intel didn't have anything to do with the MIPS specification...
In the case of OHCI, this fix is simpler than with EHCI since the two u16 fields could just be treated as if they were one le32 field. (I think MSFT was toying with non-x86 CPUs back then.) Feel free to submit patches, for 2.6 (first) and 2.4, to fix this.
- Dave
------------------------------------------------------- This SF.net email is sponsored by: The SF.net Donation Program. Do you like what SourceForge.net is doing for the Open Source Community? Make a contribution, and help us add new features and functionality. Click here: http://sourceforge.net/donate/ _______________________________________________ [EMAIL PROTECTED] To unsubscribe, use the last form field at: https://lists.sourceforge.net/lists/listinfo/linux-usb-devel
