> Huh, I thought those were guaranteed to return values in native byte
> order on PCI ... something seems screwey there, it's not as if any
> PCI device will treat bit 0 in its registers as MSB or LSB depending
> on what kind of host you've got.

readl/writel will byteswap on big-endian architectures since PCI is
a little endian bus. That works fine for "normal" PCI OHCIs. However,
this chip also has an on-chip non-PCI OHCI which happens to be mapped
big endian.

In order to deal with both a PCI OHCI and the on-chip one, it would
be necessary to have 2 instances of the driver built with different
register access macros (and different macros for accessing in-memory
data structures as well since those are big endian with that chip
and little endian with a PCI chip).

> Thing is, I didn't think that readl()/writel() was supposed to be
> bus-specific.

Well ... it's supposed to be PCI and extend to all MMIO in the "normal"
cases, but there isn't a simple way to deal with embedded chips like
that who mix both a PCI bus (thus little endian devices) and on-chip
big endian peripherals.

> The "no-IRQ" might be because your IRQ handler doesn't look enough
> like usb_hcd_irq(), which sets that flag as appropriate.  That may
> also trigger the 2000/sec rate.
> 
> That control timeout message isn't necessarily a problem, if it only
> happens a few times and things basically work.

Or because he didn't change the macros accessing EDs and TDs to also
work big endian...

Note: When working with that chip, in a former life, I also has cases
that appeared to show a bug in TD completion queue management, typically,
in some error cases, the faulty TD would be linked to the done queue, but
still point to the rest of the ED queue, thus actually linking the done
queue to the ED queue. Explosive result guaranteed.

Ben.




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