Hi,

Guys, the following story is specific to LH7A400 SoC.

> Yeah, it does.  A 1 micro-second delay should do it, right?
> I've also run into trouble with how picky the chip is.  For
> instance, the chip select and read signal must be deasserted
> between reads. (see Fig. 31, pg 137 of the ISP1362 manual)  If I
> just don't write, it sometimes leaves chip-select asserted.  So, I
> can write to another chip select in the mean-time to force it to
> change.

Mike, I finally got an opportunity to attach a logic
analyzer to the system bus and look at the behavior of CS,
OE, and WE signals. I learned the following.

1. The (almost) optimal timing in my board is, when I
configure the static memory controller's IDCY field to max
(0xf) and add udelay(1) only into HC_ISP1362_WRITE_ADDR.
However, with this setting I see that CS indeed remains
active for several subsequent reads/writes. An access to
another memory range relieves that problem.

2. If there is udelay(1) after every register access then
the problem of CS remaining active between register accesses
is gone (well, I haven't seen it).

3. The CS and OE signals on LH7A400 behave an unexpected
way. Namely, while CS is asserted about 5ns before OE is
asserted, the CS is also deasserted about 5ns before OE is
deasserted. I.e., these signals remain active for the same
amount of time, but just CS makes its cycle 5ns earlier than
OE. This phenomenon is independent of the WST1 setting in
BCR register.  The datasheet of isp1160 says that OE may be
deasserted before or together with CS. I have no idea,
whether this can affect the behavior of the chip. Perhaps
only somebody in Philips knows.

The WE signal works as expected. It is asserted together
with CS and deasserted 10ns before CS is deasserted.

Olav



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