Hi Philipp,

Thank you for the comprehensive overview.

> A couple of observations:
>
> (a) I find many PTDS have to be resubmitted many times before they get
> handled by the device even if they are finished submitting early in the
> frame remaining cycle.

Transfers start after subsequent SOF after the submission is
finished. Therefore, it should make no difference whether
you finish submission early or late in the frame. I remember
that from my experiments with a logic analyzer on usb bus.

I have also seen that the ptd's for control transfers have
to be resubmitted repeatedly. Maybe this is normal.

> (b) I found better results by only using the SOF interrupt for timing (still
> handle the other ints, but only on a SOF).

Could you please elaborate on what you mean by better
results here.

Olav



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