On Friday 01 April 2005 9:06 am, Alan Stern wrote:
> On Thu, 31 Mar 2005, David Brownell wrote:
> 
> > This is a case where edge triggering vs level triggering may want
> > slightly different code though, at least at the level of the IRQ
> > controller dispatch logic. 
> 
> Such code is needed in general, isn't it?

Certainly.  But in this case you're making usbcore do some dispatch,
rather than the HCD or the generic IRQ controller dispatch code.


> This is just the sort of thing 
> Russell King was worried about.  I can't imagine why the
> architecture-specific interrupt core routines don't already handle these
> issues.

Russell's issue was that the arch-*neutral* core code doesn't handle them.
And thus the "neutral" APIs exposed don't handle them ... e.g. on x86 how
does a driver say "this IRQ is low-level triggered"?  Answer:  it doesn't.
One must sacrifice small mammals to the BIOS and ACPI gods and pray that
the boot-time IRQ config oracles deign to produce the correct answers.

The functionality in <asm-arm/mach/irq.h> irqchip isn't really specific
to the ARM architecture, for example.  I think the reason it came up
first there is that there are so many different ARM-based chips, with
each vendor providing their own IRQ controllers.  There's a lot more
flexibility there than the usual x86 PIC/APIC/IOAPIC setup, and with
no confusion about who sets it up (never a BIOS, always Linux).


> Then there's an additional level of confusion related to whether the edge- 
> vs. level-triggering refers to the signals being sent to the interrupt 
> controller or to the signals within the peripheral controller itself.

They exist at both levels.  There are also awkward cases like chips
using level-sensitive IRQs getting hooked up to GPIO IRQ controllers that
report edge triggered GPIO IRQs, which then hook up to top-level dispatchers
that know the GPIO controller IRQs themselves are only level triggered...

- Dave




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