Hi, On Thu, 14 Apr 2005, Alan Stern wrote: > Is it true then, on all architectures, that the hardware will complete the > outw() _before_ the CPU executes the udelay() routine, even without the > mb()? > > Or does it not really matter, because the outw() will complete within a > handful of CPU cycles anyway, long before the 10 us delay is over? > > I want to avoid pathological situations where the hardware reorders the > I/O write to occur _after_ the delay loop. Apparently some architectures > have very loose ordering guarantees for I/O operations with respect to > memory operations. > I've had exactly this pathological situation on a PXA255 with my recently posted ISP1362 driver. The chip requires a delay of max. 462ns between certain register accesses. When filling the chips fifo and subsequently trying to write another register, the processor was still busy with the last fifo writes while the delay loop that should guarantee the timing timed out, resulting in the subsequent write being too early for the chip.
I solved this problem with a read of a non-cached memory area which only completes after all writes have been done (and automagically ensures the necessary delay). Lothar Wassmann ------------------------------------------------------- SF email is sponsored by - The IT Product Guide Read honest & candid reviews on hundreds of IT Products from real users. Discover which products truly live up to the hype. Start reading now. http://ads.osdn.com/?ad_id=6595&alloc_id=14396&op=click _______________________________________________ linux-usb-devel@lists.sourceforge.net To unsubscribe, use the last form field at: https://lists.sourceforge.net/lists/listinfo/linux-usb-devel
