Andre Renaud writes: > On Fri, 2005-04-22 at 09:21 +0200, Lothar Wassmann wrote: > > What type of memory access do you use? I'm using VLIO with the MSC > > setting 0x7f8c at 99.53MHz memclk. This is probably the only setup > > that can guarantee the chips timing requirements. > > > > Be aware that VLIO uses nPWE instead of nWE as write strobe. > > How are you connecting the ISP1362 up to the RDY signal on the PXA for > VLIO mode access? > There is no need to use RDY for additional wait cycles at a memclock of 99.53MHz, so the signal is pulled high via a pullup resistor.
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