On Wed, 27 Jul 2005, Pete Zaitcev wrote: > Anyway, there's nothing wrong with the string fetch. My current hypothesis > is that the particular UHCI silicon does not like when TDs go from page > to page. Here's now the linkage looks: > > uhci_hcd 0000:00:1d.3: uhci_result_control: failed with status 440000 > [ffff810000647300] link (00647242) element (00646060) > Element != First TD > 0: [ffff81000069c000] link (0069c060) e3 LS Length=7 MaxLen=7 DT0 EndPt=0 > Dev=3, PID=2d(SETUP) (buf=064cb000) > 1: [ffff81000069c060] link (0069cd80) e3 SPD LS Length=7 MaxLen=7 DT1 > EndPt=0 Dev=3, PID=69(IN) (buf=064cb800) > 2: [ffff81000069cd80] link (0069cde0) e3 SPD LS Length=7 MaxLen=7 DT0 > EndPt=0 Dev=3, PID=69(IN) (buf=064cb808) > 3: [ffff81000069cde0] link (0069ce40) e3 SPD LS Length=7 MaxLen=7 DT1 > EndPt=0 Dev=3, PID=69(IN) (buf=064cb810) > 4: [ffff81000069ce40] link (0069cea0) e3 SPD LS Length=7 MaxLen=7 DT0 > EndPt=0 Dev=3, PID=69(IN) (buf=064cb818) > 5: [ffff81000069cea0] link (0069cf00) e3 SPD LS Length=7 MaxLen=7 DT1 > EndPt=0 Dev=3, PID=69(IN) (buf=064cb820) > 6: [ffff81000069cf00] link (0069cf60) e3 SPD LS Length=7 MaxLen=7 DT0 > EndPt=0 Dev=3, PID=69(IN) (buf=064cb828) > 7: [ffff81000069cf60] link (00646060) e3 SPD LS Length=7 MaxLen=7 DT1 > EndPt=0 Dev=3, PID=69(IN) (buf=064cb830) > 8: [ffff810000646060] link (006460c0) e0 SPD LS Stalled CRC/Timeo > Length=7ff MaxLen=7 DT0 EndPt=0 Dev=3, PID=69(IN) (buf=064cb838) > 9: [ffff8100006460c0] link (00646120) e3 SPD LS Active Length=0 MaxLen=7 > DT1 EndPt=0 Dev=3, PID=69(IN) (buf=064cb840) > 10: [ffff810000646120] link (00646180) e3 SPD LS Active Length=0 MaxLen=7 > DT0 EndPt=0 Dev=3, PID=69(IN) (buf=064cb848) > [skipped 22 active TD's] > 33: [ffff8100006469c0] link (00000001) e3 LS IOC Active Length=0 MaxLen=7ff > DT1 EndPt=0 Dev=3, PID=e1(OUT) (buf=00000000) > > It always (from what I saw) breaks when TD is at a different page. > In case above is's 646000.
You may be right. If the controller didn't send the IN packet to the bus then it would fail in exactly this way. Notice however that the TD entry _was_ updated to have "Stalled CRC/Timeo" status; this means that the controller was able to access the TD even though it was on a different page from the previous one. I don't know what can be done to fix this, if your guess is correct. The other possibility is that the device can't handle the long transfer. If you always see the error occurring at a page change, and this is at different spots in the transfer for different tests, then the device isn't at fault. Alan Stern ------------------------------------------------------- SF.Net email is Sponsored by the Better Software Conference & EXPO September 19-22, 2005 * San Francisco, CA * Development Lifecycle Practices Agile & Plan-Driven Development * Managing Projects & Teams * Testing & QA Security * Process Improvement & Measurement * http://www.sqe.com/bsce5sf _______________________________________________ [email protected] To unsubscribe, use the last form field at: https://lists.sourceforge.net/lists/listinfo/linux-usb-devel
