David Brownell wrote:
Darn, I was hoping ... solving that one seems like it may need a
PCI analyser. Either there's some bizarre path where the driver
is turning that schedule on/off, or the controller itself is doing
that. Unless there's a clue somewhere in an email I've not yet read,
then I'm out of ideas for that one.
I just stuck a:
#define writel(val, addr) do { printk(KERN_INFO "!!! %s\n",
__FUNCTION__); *(volatile unsigned int *) addr = val; } while (0)
in ehci-hcd.c. Very noisy obviously, but once things settle and the
external drive is just switched off, I do _not_ get any printk's, while
I still experience the IDE throughput drop. I guess this firmly points
to chip?
On the other hand, I can switch on the external drive without any bad
effects on IDE throughput as long a ehci-hcd is not loaded. Only once
ehci-hcd loads does trouble begin, and only after unloading it does it
end. This would seem to point to ehci-hcd again...
Some weird initialization value somewhere maybe? Do you have a contact
at VIA who could maybe tell you about an undocumented bit somewhere you
could flip? Would there be any sort of effect like "being faster to the
bus" with the chip doing that async toggle? The chip's fast in benchmarks...
Rene.
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