On Saturday 03 June 2006 12:17 am, Paul Serice wrote:
> The workaround in commit f7201c3dcd7799f2aa3d6ec427b194225360ecee
> broke. The work around requires memory for DMA transfers for some
> NVidia EHCI controllers to be below 2GB, but recent changes have
> caused the DMA memory to be allocated before the DMA mask is set.
>
> Signed-off-by: Paul Serice <[EMAIL PROTECTED]>
Signed-off-by: David Brownell <[EMAIL PROTECTED]>
... Greg, this might be a good candidate for 2.6.17 still ...
> ---
>
> drivers/usb/host/ehci-pci.c | 51
> ++++++++++++++++++++-----------------------
> 1 files changed, 24 insertions(+), 27 deletions(-)
>
> d844399ebad91e3b0415b3de479be17687d2544a
> diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
> index a1bd2be..82bea65 100644
> --- a/drivers/usb/host/ehci-pci.c
> +++ b/drivers/usb/host/ehci-pci.c
> @@ -76,6 +76,30 @@ static int ehci_pci_setup(struct usb_hcd
> dbg_hcs_params(ehci, "reset");
> dbg_hcc_params(ehci, "reset");
>
> + /* ehci_init() causes memory for DMA transfers to be
> + * allocated. Thus, any vendor-specific workarounds based on
> + * limiting the type of memory used for DMA transfers must
> + * happen before ehci_init() is called. */
> + switch (pdev->vendor) {
> + case PCI_VENDOR_ID_NVIDIA:
> + /* NVidia reports that certain chips don't handle
> + * QH, ITD, or SITD addresses above 2GB. (But TD,
> + * data buffer, and periodic schedule are normal.)
> + */
> + switch (pdev->device) {
> + case 0x003c: /* MCP04 */
> + case 0x005b: /* CK804 */
> + case 0x00d8: /* CK8 */
> + case 0x00e8: /* CK8S */
> + if (pci_set_consistent_dma_mask(pdev,
> + DMA_31BIT_MASK) < 0)
> + ehci_warn(ehci, "can't enable NVidia "
> + "workaround for >2GB RAM\n");
> + break;
> + }
> + break;
> + }
> +
> /* cache this readonly data; minimize chip reads */
> ehci->hcs_params = readl(&ehci->caps->hcs_params);
>
> @@ -88,8 +112,6 @@ static int ehci_pci_setup(struct usb_hcd
> if (retval)
> return retval;
>
> - /* NOTE: only the parts below this line are PCI-specific */
> -
> switch (pdev->vendor) {
> case PCI_VENDOR_ID_TDI:
> if (pdev->device == PCI_DEVICE_ID_TDI_EHCI) {
> @@ -105,31 +127,6 @@ static int ehci_pci_setup(struct usb_hcd
> goto done;
> }
> break;
> - case PCI_VENDOR_ID_NVIDIA:
> - switch (pdev->device) {
> - /* NVidia reports that certain chips don't handle
> - * QH, ITD, or SITD addresses above 2GB. (But TD,
> - * data buffer, and periodic schedule are normal.)
> - */
> - case 0x003c: /* MCP04 */
> - case 0x005b: /* CK804 */
> - case 0x00d8: /* CK8 */
> - case 0x00e8: /* CK8S */
> - if (pci_set_consistent_dma_mask(pdev,
> - DMA_31BIT_MASK) < 0)
> - ehci_warn(ehci, "can't enable NVidia "
> - "workaround for >2GB RAM\n");
> - break;
> - /* Some NForce2 chips have problems with selective suspend;
> - * fixed in newer silicon.
> - */
> - case 0x0068:
> - pci_read_config_dword(pdev, PCI_REVISION_ID, &temp);
> - if ((temp & 0xff) < 0xa4)
> - ehci->no_selective_suspend = 1;
> - break;
> - }
> - break;
> }
>
> if (ehci_is_TDI(ehci))
> --
> 1.3.2
>
>
>
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