Hi Alan and David, First of all let me thank both of you for replying to my mail.
This is what the datasheet of Intel's IXP465 say for the Embedded TT. "IXP465 USB host supports directly connected full and low speed devices without requiring a companion controller by including the capabilities of a USB 2.0 high-speed hub transaction translator. Although there is no separate Transaction Translator block in the system, the transaction translator function normally associated with a high-speed hub has been implemented within the DMA and Protocol engine blocks. The embedded transaction translator function is an extension to EHCI interface, but makes use of the standard data structures and operational models that exist in the EHCI specification to support full and low speed devices." (1) Can there be a problem in the DMA engine, which is not transmitting my descriptor requests to the device? I do not have any programmable register to start the DMA or to initialize it. Alan- ============ About Bus trace. ============ I use the Ellisys USB analyzer (hardware) to capture the USB packets on the bus. The analyzer shows the following packets. -> Reset -> High Speed Detection Handshake (Timeout) [The device properly generates the High Speed Chirp but no response from host, as the host does not support High Speed] -> SOF packets. -> Suspended State At this point as per the bus enumeration sequence I should get the Device Descriptor request on the bus. The USB analyzer does not capture this request. Moreover I have traced the Linux core code for the USB and it seems that the request gets timed out and then aborted and removed from the queue. This is why I believe its not captured by the analyzer. Dave- I do not know much about the hardware problems that could be there but I have the Intel's IXP465 development platform board with me, which I use to test the USB driver. Shall I suspect this? I have checked about the transceiver. There is USB 2.0 LS/FS transceiver, which is available on chip (IXP465). There is a bit for selecting parallel transceiver but again this is a read only bit. It selects Serial FS transceiver by default. (2) I have the SOF packets occurring on the bus. Does this make sure that the DMA engine is working fine? (3) If the SOF's are occurring on the bus then what could be the reason for the device descriptor request not being sent out on the bus? Please let me know if you have any ideas after reading my long descriptions. It will be really very helpful to me approaching further in this issue. Thanks and Regards, Maulik Mankad -----Original Message----- From: David Brownell [mailto:[EMAIL PROTECTED] Sent: Wednesday, June 21, 2006 11:31 PM To: linux-usb-devel@lists.sourceforge.net Cc: Alan Stern; Maulik Mankad Subject: Re: [linux-usb-devel] EHCI IXDP465 USB Host :- : device not accepting address 3, error -110 On Wednesday 21 June 2006 7:54 am, Alan Stern wrote: > [Thread moved to linux-usb-devel, which seems more appropriate] > > (2) My USB host controller is EHCI compliant. Although it supports only full and > > low speed mode. There are neither transaction translators nor companion > > controllers available with the USB host. > > This sounds backward. EHCI supports only high speed, not full or low > speed. If the host doesn't have full-speed capability then it is not > USB-2.0 compliant. In fact I thought the deal was that it used the ARC core with a so-called "integrated TT" ... that is, root ports can do all three types of USB signaling directly, so a TT isn't _needed_ except to talk to FS/LS peripherals through external hubs. > > (5) The host is not able to set the address of the device. This request also > > times out with error "usb 1-1: device not accepting address 3, error -110". > ... > > What does a bus trace reveal? ... and are you even certain that the signaling lines (D+/D-) are behaving correctly? They could be mis-wired on the board, or the transceiver (integrated? external?) may not have been initialized correctly. Is there a high speed PLL that needs to be set up so that the SIE can work? Explicit PHY power up/down? Maybe you have VBUS/Vsess level comparators that need to be activated? Or even just a separate transceiver enable/disable bit. All those sorts of things are common with embedded hardware. It's rather suggestive that you don't seem to be able to get the high speed "chirp" response after a reset, making you think that having an EHCI that doesn't talk high speed makes sense. - Dave eInfochips Business Disclaimer: This message may contain confidential, proprietary or legally Privileged information. In case you are not the original intended Recipient of the message, you must not, directly or indirectly, use, Disclose, distribute, print, or copy any part of this message and you are requested to delete it and inform the sender. Any views expressed in this message are those of the individual sender unless otherwise stated. Nothing contained in this message shall be construed as an offer or acceptance of any offer by eInfochips Limited and/or eInfochips Inc("eInfochips") unless sent with that express intent and with due authority of eInfochips. eInfochips has taken enough precautions to prevent the spread of viruses. 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