On Thursday 12 April 2007 8:51 am, [EMAIL PROTECTED] wrote:
> Hayes, Stuart wrote:
> > EHCI controllers that don't cache enough microframes can get MMF
> > errors when CPU frequency changes occur between the start and
> > completion of split interrupt transactions, due to delays in reading
> > main memory (caused by CPU cache snoop delays).   
> > 
> > This patch adds a cpufreq notifier to the EHCI driver that will
> > inactivate split interrupt transactions during frequency transitions.
> > It was tested on Intel ICH7 and Serverworks/Broadcom HT1000 EHCI
> > controllers.   
> > 
> > Signed-off-by: Stuart Hayes <[EMAIL PROTECTED]>
> 
> 
> Does the lack of response mean that this patch won't be accepted? 

No.  I've been running it on my laptop for a few days now -- albeit without
lowspeed devices -- and was expecting to take the next step (final review
of the code, before forwarding it to Greg) soon.  Maybe today even.  I was
just thinking about this yesterday, in fact.

This one seems easier to approve than the one adding support for curious
byte ordering in various vendors' EHCI silicon.  ;)

- Dave


> Is there anything I could do to make it more acceptable?  There's
> definitely an issue that this addresses... if this patch isn't good for
> some reason I'll be happy to try another approach.  The only other thing
> I can think of--other than setting the I bit--is to unlink all of the
> split interrupt QHs during CPU frequency transitions.
> 
> Or... I could add a kernel parameter so that this patch wouldn't be
> enabled by default, so that only users who are seeing the problem could
> turn it on... that way this could get some wider testing without risk of
> everybody's USB subsystems failing mysteriously...
> 
> Thanks
> Stuart
> 

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