> So on processors which do not guarantee the order of writes we should
> insert memory barriers before writing the cmdStatus register because the
> writes to TDs and EDs might still not have been done, right? Currently
Right
> there's quite a lot of code after the last change to TD in td_fill
> and before HC starts processing the transfer lists so I think we are safe
> but I'm sure this should be done - atleast for the sake of correctness.
PCI posting also takes time and will delay the cmdStatus write until the next
read from the pci or the posting timeout expiring.
As an aside I see nothing that forbids the OHCI controller from issuing
speculative reads either
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