On Wed, Mar 22, 2000, Bob Cutler <[EMAIL PROTECTED]> wrote:
>Here's the story on the Unrecoverable Error interrupt (UE) on the USS-312.
>
>The Unrecoverable Error (EU) is caused by either a PCI Master Abort or a PCI
>Target Abort.
>
>The PCI Master Abort occurs when the Host Controller Latency Timer has
expired
>and the intended transaction has not concluded. This could happen if the
value
>in the Latency Timer Register is too small. A typical value for the Latency
>Timer Register is 16 (10h). Another case when a Master Abort could occur is
>when the Host Controller is trying to read a location in Host Memory
that does
>not result in DEVSEL being asserted. Perhaps, the EDs+TDs are pointing to a
>section in Memory that is not valid.
>
>The PCI Target Abort indicates that the target requires the transaction to be
>stopped. This could be caused by the Host Controller not understanding
what it
>needs to do. Perhaps, there is a parity error or something that the Host
>Controller does not know how to respond to, so it responds with a Target
>Abort.
Well, that's definitely interesting, since it looks somewhat related to
the corrupt donelist we have on some PPC. I didn't run the patch with the
test for EU yet, I'll try this next week-end.
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