diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index d43daf8..0a33a1d 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -50,6 +50,7 @@ #include #include +#include #include #include @@ -69,6 +70,113 @@ MODULE_PARM_DESC(maximum_speed, "Maximum supported speed."); static DECLARE_BITMAP(dwc3_devs, DWC3_DEVS_POSSIBLE); +static void __devinit dwc3_cache_hwparams(struct dwc3 *dwc) +{ + struct dwc3_hwparams *parms = &dwc->hwparams; + + parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); + parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); + parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); + parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); + parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); + parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); + parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); + parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); + parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); +} + +/** + * dwc3_core_soft_reset - Issues core soft reset and PHY reset + * @dwc: pointer to our context structure + */ +static void dwc3_core_soft_reset(struct dwc3 *dwc) +{ + u32 reg; + + /* Before Resetting PHY, put Core in Reset */ + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + reg |= DWC3_GCTL_CORESOFTRESET; + dwc3_writel(dwc->regs, DWC3_GCTL, reg); + + /* Assert USB3 PHY reset */ + reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); + reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); + + /* Assert USB2 PHY reset */ + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); + reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); + + mdelay(100); + + /* Clear USB3 PHY reset */ + reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); + reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); + + /* Clear USB2 PHY reset */ + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); + reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); + + /* After PHYs are stable we can take Core out of reset state */ + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + reg &= ~DWC3_GCTL_CORESOFTRESET; + dwc3_writel(dwc->regs, DWC3_GCTL, reg); +} + +static int dwc3_core_reset(struct dwc3 *dwc) +{ + unsigned long timeout; + u32 reg; + + dwc3_core_soft_reset(dwc); + + /* issue device SoftReset too */ + timeout = jiffies + msecs_to_jiffies(500); + dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); + do { + reg = dwc3_readl(dwc->regs, DWC3_DCTL); + if (!(reg & DWC3_DCTL_CSFTRST)) + break; + + if (time_after(jiffies, timeout)) { + dev_err(dwc->dev, "Reset Timed Out\n"); + return -ETIMEDOUT; + } + + cpu_relax(); + } while (true); + + dwc3_cache_hwparams(dwc); + + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + reg &= ~DWC3_GCTL_SCALEDOWN_MASK; + reg &= ~DWC3_GCTL_DISSCRAMBLE; + + switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { + case DWC3_GHWPARAMS1_EN_PWROPT_CLK: + reg &= ~DWC3_GCTL_DSBLCLKGTNG; + break; + default: + dev_dbg(dwc->dev, "No power optimization available\n"); + } + + /* + * WORKAROUND: DWC3 revisions <1.90a have a bug + * where the device can fail to connect at SuperSpeed + * and falls back to high-speed mode which causes + * the device to enter a Connect/Disconnect loop + */ + if (dwc->revision < DWC3_REVISION_190A) + reg |= DWC3_GCTL_U2RSTECN; + + dwc3_writel(dwc->regs, DWC3_GCTL, reg); + + return 0; +} + int dwc3_get_device_id(void) { int id; @@ -113,46 +221,7 @@ void dwc3_set_mode(struct dwc3 *dwc, u32 mode) dwc3_writel(dwc->regs, DWC3_GCTL, reg); } -/** - * dwc3_core_soft_reset - Issues core soft reset and PHY reset - * @dwc: pointer to our context structure - */ -static void dwc3_core_soft_reset(struct dwc3 *dwc) -{ - u32 reg; - - /* Before Resetting PHY, put Core in Reset */ - reg = dwc3_readl(dwc->regs, DWC3_GCTL); - reg |= DWC3_GCTL_CORESOFTRESET; - dwc3_writel(dwc->regs, DWC3_GCTL, reg); - - /* Assert USB3 PHY reset */ - reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); - reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; - dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); - - /* Assert USB2 PHY reset */ - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); - reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); - - mdelay(100); - - /* Clear USB3 PHY reset */ - reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); - reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; - dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); - - /* Clear USB2 PHY reset */ - reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); - reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; - dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); - /* After PHYs are stable we can take Core out of reset state */ - reg = dwc3_readl(dwc->regs, DWC3_GCTL); - reg &= ~DWC3_GCTL_CORESOFTRESET; - dwc3_writel(dwc->regs, DWC3_GCTL, reg); -} /** * dwc3_free_one_event_buffer - Frees one event buffer @@ -292,21 +361,6 @@ static void dwc3_event_buffers_cleanup(struct dwc3 *dwc) } } -static void __devinit dwc3_cache_hwparams(struct dwc3 *dwc) -{ - struct dwc3_hwparams *parms = &dwc->hwparams; - - parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0); - parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1); - parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2); - parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3); - parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4); - parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5); - parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6); - parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7); - parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8); -} - /** * dwc3_core_init - Low-level initialization of DWC3 Core * @dwc: Pointer to our controller context structure @@ -328,49 +382,10 @@ static int __devinit dwc3_core_init(struct dwc3 *dwc) } dwc->revision = reg; - dwc3_core_soft_reset(dwc); + ret = dwc3_core_reset(dwc); - /* issue device SoftReset too */ - timeout = jiffies + msecs_to_jiffies(500); - dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST); - do { - reg = dwc3_readl(dwc->regs, DWC3_DCTL); - if (!(reg & DWC3_DCTL_CSFTRST)) - break; - - if (time_after(jiffies, timeout)) { - dev_err(dwc->dev, "Reset Timed Out\n"); - ret = -ETIMEDOUT; - goto err0; - } - - cpu_relax(); - } while (true); - - dwc3_cache_hwparams(dwc); - - reg = dwc3_readl(dwc->regs, DWC3_GCTL); - reg &= ~DWC3_GCTL_SCALEDOWN_MASK; - reg &= ~DWC3_GCTL_DISSCRAMBLE; - - switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) { - case DWC3_GHWPARAMS1_EN_PWROPT_CLK: - reg &= ~DWC3_GCTL_DSBLCLKGTNG; - break; - default: - dev_dbg(dwc->dev, "No power optimization available\n"); - } - - /* - * WORKAROUND: DWC3 revisions <1.90a have a bug - * where the device can fail to connect at SuperSpeed - * and falls back to high-speed mode which causes - * the device to enter a Connect/Disconnect loop - */ - if (dwc->revision < DWC3_REVISION_190A) - reg |= DWC3_GCTL_U2RSTECN; - - dwc3_writel(dwc->regs, DWC3_GCTL, reg); + if (ret < 0) + goto err0; ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE); if (ret) { @@ -594,12 +609,165 @@ static int __devexit dwc3_remove(struct platform_device *pdev) return 0; } +#if 1 +int dwc3_core_reg_print(struct device *dev) +{ + struct dwc3 *dwc; + + dwc = dev_get_drvdata(dev); + + if (!dwc) + return -1; + + printk(" DWC3_GTXFIFOSIZ(0) = %x \n", dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(0))); + printk(" DWC3_GRXFIFOSIZ(0) = %x \n", dwc3_readl(dwc->regs, DWC3_GRXFIFOSIZ(0))); + printk(" DWC3_GTXTHRCFG = %x \n", dwc3_readl(dwc->regs, DWC3_GTXTHRCFG)); + printk(" DWC3_GRXTHRCFG = %x \n", dwc3_readl(dwc->regs, DWC3_GRXTHRCFG)); + printk(" DWC3_GPRTBIMAP_HS0 = %x \n", dwc3_readl(dwc->regs, DWC3_GPRTBIMAP_HS0)); + printk(" DWC3_GPRTBIMAP_FS0 = %x \n", dwc3_readl(dwc->regs, DWC3_GPRTBIMAP_FS0)); + printk(" DWC3_GPRTBIMAP_HS1 = %x \n", dwc3_readl(dwc->regs, DWC3_GPRTBIMAP_HS1)); + printk(" DWC3_GPRTBIMAP_FS1 = %x \n", dwc3_readl(dwc->regs, DWC3_GPRTBIMAP_FS1)); + printk(" DWC3_GUCTL = %x \n", dwc3_readl(dwc->regs, DWC3_GUCTL)); + printk(" DWC3_GUSB3PIPECTL(0) = %x\n", dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0))); +} +#endif + +#ifdef CONFIG_PM +static int dwc3_core_resume(struct device *dev) +{ + struct dwc3 *dwc; + int ret; + unsigned long timeout; + u32 reg; + u32 gctl; + struct clk *sclk_usbdrd30; + u32 susp_clk_freq; + + dwc = dev_get_drvdata(dev); + + if (!dwc) + return -1; + + pm_runtime_enable(dev); + pm_runtime_get_sync(dev); + pm_runtime_forbid(dev); + + printk("\n <<<< dwc3_core_resume >>>> \n"); + + ret = dwc3_core_reset(dwc); + + if (ret < 0) + return ret; + + /* Clearing the SUSPEND State */ + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); + reg &= ~(DWC3_GUSB2PHYCFG_SUSPHY | DWC3_GUSB2PHYCFG_EnblSlpM | (0xf << 10)); + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); + + /* Set the USB turn around */ + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); + reg |= ( 0x9 << 10); + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); + + reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); + reg &= ~DWC3_GUSB3PIPECTL_SUSPHY; + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); + + /* Global core init */ + dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, (DWC3_GSBUSCFG0_INCR16BrstEna | + DWC3_GSBUSCFG0_INCR8BrstEna | + DWC3_GSBUSCFG0_INCR4BrstEna)); + + dwc3_writel(dwc->regs, DWC3_GSBUSCFG1, DWC3_GSBUSCFG1_BREQLIMIT(0x3)); + +#if 1 + sclk_usbdrd30 = clk_get(dev, "sclk_usbdrd30"); + if (IS_ERR(sclk_usbdrd30)) { + printk(" <<< Failed to get sclk_usbdrd30 clock >>>> \n"); + return ; + } + + susp_clk_freq = clk_get_rate(sclk_usbdrd30); + /* suspend clk should be set between 32 kHz and 125 MHz */ + if (susp_clk_freq < 32000 || susp_clk_freq > 125000000) { + return ; + } + + /* Power Down Scale = suspend_clk_freq / 16kHz */ + gctl = dwc3_readl(dwc->regs , DWC3_GCTL); + gctl &= ~(3 << 6 | 1 << 3 | (0x1FFF << 19)); + + gctl |= (((susp_clk_freq/16000) << 19) | (0x1 << 6) | /* Ram Clock Select */ (1 << 16)); + + dwc3_writel(dwc->regs , DWC3_GCTL, gctl); +#endif + + //dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, 0x0); + //dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, 0x0); + + switch (dwc->mode) { + case DWC3_MODE_DEVICE: + dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE); + break; + case DWC3_MODE_HOST: + dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST); + break; + case DWC3_MODE_DRD: + dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG); + } + + pm_runtime_allow(dev); + + dwc3_core_reg_print(dev); + + return 0; +} + +static int dwc3_core_suspend(struct device *dev) +{ + u32 reg; + struct dwc3 *dwc; + + dwc = dev_get_drvdata(dev); + if (!dwc) + return -1; + + pm_runtime_put(dev); + pm_runtime_disable(dev); + + printk("\n <<<< dwc3_core_suspend >>>> \n"); + + dwc3_core_reg_print(dev); + + reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); + reg |= (DWC3_GUSB2PHYCFG_SUSPHY | DWC3_GUSB2PHYCFG_EnblSlpM); + dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); + + reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); + reg |= DWC3_GUSB3PIPECTL_SUSPHY; + dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); + + reg = dwc3_readl(dwc->regs, DWC3_GCTL); + reg |= DWC3_GCTL_HIBERNATE; + dwc3_writel(dwc->regs, DWC3_GCTL, reg); + + return 0; +} + +static const struct dev_pm_ops dwc3_core_pm_ops = { + .suspend = dwc3_core_suspend, + .resume = dwc3_core_resume, +}; +#endif static struct platform_driver dwc3_driver = { .probe = dwc3_probe, .remove = __devexit_p(dwc3_remove), .driver = { .name = "dwc3", +#ifdef CONFIG_PM + .pm = &dwc3_core_pm_ops, +#endif }, }; diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 42d0abc..5310408 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -175,11 +175,19 @@ #define DWC3_GCTL_SCALEDOWN_MASK DWC3_GCTL_SCALEDOWN(3) #define DWC3_GCTL_DISSCRAMBLE (1 << 3) #define DWC3_GCTL_DSBLCLKGTNG (1 << 0) +#define DWC3_GCTL_HIBERNATE (1 << 1) + +#define DWC3_GSBUSCFG0_INCR16BrstEna (1 << 3) +#define DWC3_GSBUSCFG0_INCR8BrstEna (1 << 2) +#define DWC3_GSBUSCFG0_INCR4BrstEna (1 << 1) +#define DWC3_GSBUSCFG1_BREQLIMIT(_x) ((_x) << 8) /* Global USB2 PHY Configuration Register */ #define DWC3_GUSB2PHYCFG_PHYSOFTRST (1 << 31) #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) +#define DWC3_GUSB2PHYCFG_EnblSlpM (1 << 8) + /* Global USB3 PIPE Control Register */ #define DWC3_GUSB3PIPECTL_PHYSOFTRST (1 << 31) #define DWC3_GUSB3PIPECTL_SUSPHY (1 << 17) diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c index 4f95bdf..34cc2b3 100644 --- a/drivers/usb/dwc3/dwc3-exynos.c +++ b/drivers/usb/dwc3/dwc3-exynos.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -178,12 +179,73 @@ static const struct of_device_id exynos_xhci_match[] = { MODULE_DEVICE_TABLE(of, exynos_xhci_match); #endif + +#ifdef CONFIG_PM +static int dwc3_exynos_suspend(struct device *dev) +{ + struct dwc3_exynos_data *pdata = dev->platform_data; + struct dwc3_exynos *exynos; + struct platform_device *pdev = to_platform_device(dev); + + exynos = dev_get_drvdata(dev); + + if (!exynos) + return -1; + + if(pm_runtime_suspended(dev)) + return 0; + + if (pdata && pdata->phy_exit) + pdata->phy_exit(pdev, pdata->phy_type); + + clk_disable(exynos->clk); + + return 0; +} + +static int dwc3_exynos_resume(struct device *dev) +{ + struct dwc3_exynos_data *pdata = dev->platform_data; + struct dwc3_exynos *exynos; + struct platform_device *pdev = to_platform_device(dev); + + exynos = dev_get_drvdata(dev); + + if (!exynos) + return -1; + + pm_runtime_resume(dev); + + dwc3_setup_vbus_gpio(pdev); + + clk_enable(exynos->clk); + + /* PHY initialization */ + if (!pdata) { + dev_dbg(&pdev->dev, "missing platform data\n"); + } else { + if (pdata->phy_init) + pdata->phy_init(pdev, pdata->phy_type); + } + + return 0; +} + +static const struct dev_pm_ops dwc3_exynos_pm_ops = { + .suspend = dwc3_exynos_suspend, + .resume = dwc3_exynos_resume, +}; +#endif + static struct platform_driver dwc3_exynos_driver = { .probe = dwc3_exynos_probe, .remove = __devexit_p(dwc3_exynos_remove), .driver = { .name = "exynos-dwc3", .of_match_table = of_match_ptr(exynos_xhci_match), +#ifdef CONFIG_PM + .pm = &dwc3_exynos_pm_ops, +#endif }, }; diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c index ab756ab..d7a223a 100644 --- a/drivers/usb/host/xhci-plat.c +++ b/drivers/usb/host/xhci-plat.c @@ -182,11 +182,58 @@ static int xhci_plat_remove(struct platform_device *dev) return 0; } +#ifdef CONFIG_PM +static int xhci_plat_suspend(struct device *dev) +{ + struct usb_hcd *hcd; + struct xhci_hcd *xhci; + + printk(" <<<< function %s line %d >>>> \n",__func__,__LINE__); + + hcd = dev_get_drvdata(dev); + if (!hcd) + return -EINVAL; + + xhci = hcd_to_xhci(hcd); + + if (hcd->state != HC_STATE_SUSPENDED || + xhci->shared_hcd->state != HC_STATE_SUSPENDED) + return -EINVAL; + + return xhci_suspend(xhci); +} + +static int xhci_plat_resume(struct device *dev) +{ + struct usb_hcd *hcd; + struct xhci_hcd *xhci; + + printk(" <<<< function %s line %d >>>> \n",__func__,__LINE__); + + hcd = dev_get_drvdata(dev); + + if (!hcd) + return -EINVAL; + + xhci = hcd_to_xhci(hcd); + + return xhci_resume(xhci, 0); +} + +static const struct dev_pm_ops xhci_plat_pm_ops = { + .suspend = xhci_plat_suspend, + .resume = xhci_plat_resume, +}; +#endif + static struct platform_driver usb_xhci_driver = { .probe = xhci_plat_probe, .remove = xhci_plat_remove, .driver = { .name = "xhci-hcd", +#ifdef CONFIG_PM + .pm = &xhci_plat_pm_ops, +#endif }, }; MODULE_ALIAS("platform:xhci-hcd");