On Mon, 2018-12-10 at 14:08 -0800, Thinh Nguyen wrote:
> Synopsys USB 3.x host HAPS platform has a class code of
> PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these
> devices should use dwc3-haps driver. Change these devices' class code to
> PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming
> them.
>
> +
> + switch (pdev->device) {
> + case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3:
> + case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI:
> + case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31:
> + pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
> + pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3
> driver can claim this instead of xhci\n",
> + class, pdev->class);
> + break;
> + default:
> + return;
> + }
> +}
> +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID,
> + quirk_synopsys_haps);
> +
This change breaks my IMX7d based device. This SoC has a PCIe bus
based on the Synopsys Designware host controller. This has a root
bridge that shows up as:
00:00.0 PCI bridge: Synopsys, Inc. Device abcd (rev 01) (prog-if 00 [Normal
decode])
00:00.0 0604: 16c3:abcd (rev 01) (prog-if 00 [Normal decode])
Which is to say, class 0x0604, vendor PCI_VENDOR_ID_SYNOPSYS, and the
device ID 0xabcd.
It looks like there has been a bit of sloppy allocation of PCI device
codes, as PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3 is also 0xabcd.
So the result of this patch is to try to turn the imx7d PCIe root
bridge into a USB controller. Which of course breaks it and prevents
anything behind it, i.e. the endpoint attached to the pci-e bus, from
working.
Somehow this quirk needs to be more targeted.
