[  180.336335] hub 1-2:1.0: state 7 ports 4 chg 0000 evt 0002
[  180.336429] usb 1-2-port1: status 0101, change 0001, 12 Mb/s
[  180.479206] usb 1-2-port1: debounce total 100ms stable 100ms status 0x101
[  180.479212] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.479237] xhci_hcd 0000:00:15.0: Slot 6 output ctx = 0xfffbd000 (dma)
[  180.479243] xhci_hcd 0000:00:15.0: Slot 6 input ctx = 0xfffae000 (dma)
[  180.479250] xhci_hcd 0000:00:15.0: Set slot id 6 dcbaa entry 000000005f82d8a6 to 0xfffbd000
[  180.559201] usb 1-2.1: new full-speed USB device number 7 using xhci_hcd
[  180.559207] xhci_hcd 0000:00:15.0: Set root hub portnum to 2
[  180.559208] xhci_hcd 0000:00:15.0: Set fake root hub portnum to 2
[  180.559211] xhci_hcd 0000:00:15.0: udev->tt = 000000005efec00d
[  180.559213] xhci_hcd 0000:00:15.0: udev->ttport = 0x1
[  180.559215] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.559232] xhci_hcd 0000:00:15.0: Successful setup context command
[  180.559235] xhci_hcd 0000:00:15.0: Op regs DCBAA ptr = 0x000000fffff000
[  180.559238] xhci_hcd 0000:00:15.0: Slot ID 6 dcbaa entry @000000005f82d8a6 = 0x000000fffbd000
[  180.559239] xhci_hcd 0000:00:15.0: Output Context DMA address = 0xfffbd000
[  180.559241] xhci_hcd 0000:00:15.0: Internal device address = 0
[  180.559357] xhci_hcd 0000:00:15.0: Waiting for status stage event
[  180.639241] xhci_hcd 0000:00:15.0: Resetting device with slot ID 6
[  180.639244] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.639252] xhci_hcd 0000:00:15.0: Completed reset device command.
[  180.639258] xhci_hcd 0000:00:15.0: Can't reset device (slot ID 6) in default state
[  180.639259] xhci_hcd 0000:00:15.0: Not freeing device rings.
[  180.639263] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.639358] xhci_hcd 0000:00:15.0: Successful setup address command
[  180.639362] xhci_hcd 0000:00:15.0: Op regs DCBAA ptr = 0x000000fffff000
[  180.639365] xhci_hcd 0000:00:15.0: Slot ID 6 dcbaa entry @000000005f82d8a6 = 0x000000fffbd000
[  180.639366] xhci_hcd 0000:00:15.0: Output Context DMA address = 0xfffbd000
[  180.639368] xhci_hcd 0000:00:15.0: Internal device address = 0
[  180.659898] usb 1-2.1: skipped 10 descriptors after interface
[  180.659900] usb 1-2.1: skipped 2 descriptors after interface
[  180.659903] usb 1-2.1: skipped 1 descriptor after endpoint
[  180.659905] usb 1-2.1: skipped 2 descriptors after interface
[  180.659906] usb 1-2.1: skipped 1 descriptor after endpoint
[  180.659908] usb 1-2.1: skipped 1 descriptor after interface
[  180.660001] xhci_hcd 0000:00:15.0: Waiting for status stage event
[  180.660014] usb 1-2.1: default language 0x0409
[  180.660150] xhci_hcd 0000:00:15.0: Waiting for status stage event
[  180.660163] usb 1-2.1: udev 7, busnum 1, minor = 6
[  180.660167] usb 1-2.1: New USB device found, idVendor=0d8c, idProduct=000c, bcdDevice= 1.00
[  180.660169] usb 1-2.1: New USB device strings: Mfr=0, Product=1, SerialNumber=0
[  180.660171] usb 1-2.1: Product: C-Media USB Headphone Set  
[  180.660327] usb 1-2.1: usb_probe_device
[  180.660330] usb 1-2.1: configuration #1 chosen from 1 choice
[  180.660352] xhci_hcd 0000:00:15.0: add ep 0x83, slot id 6, new drop flags = 0x0, new add flags = 0x80
[  180.660355] xhci_hcd 0000:00:15.0: xhci_check_bandwidth called for udev 000000009e0b7f89
[  180.660358] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.660574] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.660750] usb 1-2.1: Available LS/FS bandwidth on external hub port1 - 90 %
[  180.660754] xhci_hcd 0000:00:15.0: Available LS/FS bandwidth on external hub port1 - 90 %
[  180.660756] usb 1-2.1: Available LS/FS bandwidth on external hub port2 - 90 %
[  180.660758] xhci_hcd 0000:00:15.0: Available LS/FS bandwidth on external hub port2 - 90 %
[  180.660760] usb 1-2.1: Available LS/FS bandwidth on external hub port3 - 90 %
[  180.660762] xhci_hcd 0000:00:15.0: Available LS/FS bandwidth on external hub port3 - 90 %
[  180.660764] usb 1-2.1: Available LS/FS bandwidth on external hub port4 - 90 %
[  180.660765] xhci_hcd 0000:00:15.0: Available LS/FS bandwidth on external hub port4 - 90 %
[  180.660773] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.660948] usb 1-2: Available HS bandwidth on root hub port1 - 80 %
[  180.660952] xhci_hcd 0000:00:15.0: Available HS bandwidth on root hub port1 - 80 %
[  180.660954] usb 1-2: Available HS bandwidth on root hub port2 - 73 %
[  180.660956] xhci_hcd 0000:00:15.0: Available HS bandwidth on root hub port2 - 73 %
[  180.660958] usb 1-2: Available HS bandwidth on root hub port3 - 73 %
[  180.660960] xhci_hcd 0000:00:15.0: Available HS bandwidth on root hub port3 - 73 %
[  180.660961] usb 1-2: Available HS bandwidth on root hub port4 - 80 %
[  180.660963] xhci_hcd 0000:00:15.0: Available HS bandwidth on root hub port4 - 80 %
[  180.660967] xhci_hcd 0000:00:15.0: Successful Endpoint Configure command
[  180.660979] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.662928] xhci_hcd 0000:00:15.0: Stopped on No-op or Link TRB for slot 6 ep 6
[  180.662939] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.663233] usb 1-2.1: adding 1-2.1:1.0 (config #1, interface 0)
[  180.663268] usb 1-2.1: adding 1-2.1:1.1 (config #1, interface 1)
[  180.663292] usb 1-2.1: adding 1-2.1:1.2 (config #1, interface 2)
[  180.663319] usb 1-2.1: adding 1-2.1:1.3 (config #1, interface 3)
[  180.663352] usbhid 1-2.1:1.3: usb_probe_interface
[  180.663354] usbhid 1-2.1:1.3: usb_probe_interface - got id
[  180.663860] input: C-Media USB Headphone Set   as /devices/pci0000:00/0000:00:15.0/usb1/1-2/1-2.1/1-2.1:1.3/0003:0D8C:000C.0003/input/input6
[  180.723521] hid-generic 0003:0D8C:000C.0003: input,hidraw2: USB HID v1.00 Device [C-Media USB Headphone Set  ] on usb-0000:00:15.0-2.1/input3
[  180.762578] snd-usb-audio 1-2.1:1.0: usb_probe_interface
[  180.762584] snd-usb-audio 1-2.1:1.0: usb_probe_interface - got id
[  180.762724] xhci_hcd 0000:00:15.0: Waiting for status stage event
[  180.762843] xhci_hcd 0000:00:15.0: add ep 0x1, slot id 6, new drop flags = 0x0, new add flags = 0x4
[  180.762847] xhci_hcd 0000:00:15.0: xhci_check_bandwidth called for udev 000000009e0b7f89
[  180.762853] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.763049] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.763225] usb 1-2.1: Available LS/FS bandwidth on external hub port1 - 90 %
[  180.763228] xhci_hcd 0000:00:15.0: Available LS/FS bandwidth on external hub port1 - 90 %
[  180.763231] usb 1-2.1: Available LS/FS bandwidth on external hub port2 - 90 %
[  180.763233] xhci_hcd 0000:00:15.0: Available LS/FS bandwidth on external hub port2 - 90 %
[  180.763235] usb 1-2.1: Available LS/FS bandwidth on external hub port3 - 90 %
[  180.763236] xhci_hcd 0000:00:15.0: Available LS/FS bandwidth on external hub port3 - 90 %
[  180.763238] usb 1-2.1: Available LS/FS bandwidth on external hub port4 - 90 %
[  180.763240] xhci_hcd 0000:00:15.0: Available LS/FS bandwidth on external hub port4 - 90 %
[  180.763249] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.763469] usb 1-2: Available HS bandwidth on root hub port1 - 80 %
[  180.763472] xhci_hcd 0000:00:15.0: Available HS bandwidth on root hub port1 - 80 %
[  180.763475] usb 1-2: Available HS bandwidth on root hub port2 - 73 %
[  180.763477] xhci_hcd 0000:00:15.0: Available HS bandwidth on root hub port2 - 73 %
[  180.763479] usb 1-2: Available HS bandwidth on root hub port3 - 73 %
[  180.763481] xhci_hcd 0000:00:15.0: Available HS bandwidth on root hub port3 - 73 %
[  180.763482] usb 1-2: Available HS bandwidth on root hub port4 - 80 %
[  180.763484] xhci_hcd 0000:00:15.0: Available HS bandwidth on root hub port4 - 80 %
[  180.763489] usb 1-2.1: Not enough bandwidth for new device state.
[  180.763495] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.763694] usb 1-2.1: Available LS/FS bandwidth on external hub port1 - 90 %
[  180.763697] xhci_hcd 0000:00:15.0: Available LS/FS bandwidth on external hub port1 - 90 %
[  180.763700] usb 1-2.1: Available LS/FS bandwidth on external hub port2 - 90 %
[  180.763702] xhci_hcd 0000:00:15.0: Available LS/FS bandwidth on external hub port2 - 90 %
[  180.763704] usb 1-2.1: Available LS/FS bandwidth on external hub port3 - 90 %
[  180.763706] xhci_hcd 0000:00:15.0: Available LS/FS bandwidth on external hub port3 - 90 %
[  180.763707] usb 1-2.1: Available LS/FS bandwidth on external hub port4 - 90 %
[  180.763709] xhci_hcd 0000:00:15.0: Available LS/FS bandwidth on external hub port4 - 90 %
[  180.763718] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.763913] usb 1-2: Available HS bandwidth on root hub port1 - 80 %
[  180.763916] xhci_hcd 0000:00:15.0: Available HS bandwidth on root hub port1 - 80 %
[  180.763918] usb 1-2: Available HS bandwidth on root hub port2 - 73 %
[  180.763920] xhci_hcd 0000:00:15.0: Available HS bandwidth on root hub port2 - 73 %
[  180.763922] usb 1-2: Available HS bandwidth on root hub port3 - 73 %
[  180.763924] xhci_hcd 0000:00:15.0: Available HS bandwidth on root hub port3 - 73 %
[  180.763926] usb 1-2: Available HS bandwidth on root hub port4 - 80 %
[  180.763928] xhci_hcd 0000:00:15.0: Available HS bandwidth on root hub port4 - 80 %
[  180.763933] xhci_hcd 0000:00:15.0: xhci_reset_bandwidth called for udev 000000009e0b7f89
[  180.763952] usb 1-2.1: Not enough bandwidth for altsetting 1
[  180.764258] xhci_hcd 0000:00:15.0: xhci_check_bandwidth called for udev 000000009e0b7f89
[  180.764442] xhci_hcd 0000:00:15.0: add ep 0x82, slot id 6, new drop flags = 0x0, new add flags = 0x21
[  180.764445] xhci_hcd 0000:00:15.0: xhci_check_bandwidth called for udev 000000009e0b7f89
[  180.764449] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.764665] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.764863] usb 1-2.1: Available LS/FS bandwidth on external hub port1 - 90 %
[  180.764866] xhci_hcd 0000:00:15.0: Available LS/FS bandwidth on external hub port1 - 90 %
[  180.764869] usb 1-2.1: Available LS/FS bandwidth on external hub port2 - 90 %
[  180.764871] xhci_hcd 0000:00:15.0: Available LS/FS bandwidth on external hub port2 - 90 %
[  180.764873] usb 1-2.1: Available LS/FS bandwidth on external hub port3 - 90 %
[  180.764875] xhci_hcd 0000:00:15.0: Available LS/FS bandwidth on external hub port3 - 90 %
[  180.764877] usb 1-2.1: Available LS/FS bandwidth on external hub port4 - 90 %
[  180.764878] xhci_hcd 0000:00:15.0: Available LS/FS bandwidth on external hub port4 - 90 %
[  180.764887] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.765083] usb 1-2: Available HS bandwidth on root hub port1 - 80 %
[  180.765086] xhci_hcd 0000:00:15.0: Available HS bandwidth on root hub port1 - 80 %
[  180.765088] usb 1-2: Available HS bandwidth on root hub port2 - 73 %
[  180.765090] xhci_hcd 0000:00:15.0: Available HS bandwidth on root hub port2 - 73 %
[  180.765092] usb 1-2: Available HS bandwidth on root hub port3 - 73 %
[  180.765094] xhci_hcd 0000:00:15.0: Available HS bandwidth on root hub port3 - 73 %
[  180.765096] usb 1-2: Available HS bandwidth on root hub port4 - 80 %
[  180.765098] xhci_hcd 0000:00:15.0: Available HS bandwidth on root hub port4 - 80 %
[  180.765102] usb 1-2.1: Not enough bandwidth for new device state.
[  180.765108] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.765280] usb 1-2.1: Available LS/FS bandwidth on external hub port1 - 90 %
[  180.765283] xhci_hcd 0000:00:15.0: Available LS/FS bandwidth on external hub port1 - 90 %
[  180.765285] usb 1-2.1: Available LS/FS bandwidth on external hub port2 - 90 %
[  180.765287] xhci_hcd 0000:00:15.0: Available LS/FS bandwidth on external hub port2 - 90 %
[  180.765289] usb 1-2.1: Available LS/FS bandwidth on external hub port3 - 90 %
[  180.765291] xhci_hcd 0000:00:15.0: Available LS/FS bandwidth on external hub port3 - 90 %
[  180.765292] usb 1-2.1: Available LS/FS bandwidth on external hub port4 - 90 %
[  180.765294] xhci_hcd 0000:00:15.0: Available LS/FS bandwidth on external hub port4 - 90 %
[  180.765299] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.765468] usb 1-2: Available HS bandwidth on root hub port1 - 80 %
[  180.765470] xhci_hcd 0000:00:15.0: Available HS bandwidth on root hub port1 - 80 %
[  180.765472] usb 1-2: Available HS bandwidth on root hub port2 - 73 %
[  180.765474] xhci_hcd 0000:00:15.0: Available HS bandwidth on root hub port2 - 73 %
[  180.765476] usb 1-2: Available HS bandwidth on root hub port3 - 73 %
[  180.765478] xhci_hcd 0000:00:15.0: Available HS bandwidth on root hub port3 - 73 %
[  180.765480] usb 1-2: Available HS bandwidth on root hub port4 - 80 %
[  180.765482] xhci_hcd 0000:00:15.0: Available HS bandwidth on root hub port4 - 80 %
[  180.765485] xhci_hcd 0000:00:15.0: xhci_reset_bandwidth called for udev 000000009e0b7f89
[  180.765498] usb 1-2.1: Not enough bandwidth for altsetting 1
[  180.765731] xhci_hcd 0000:00:15.0: xhci_check_bandwidth called for udev 000000009e0b7f89
[  180.766186] xhci_hcd 0000:00:15.0: Stalled endpoint for slot 6 ep 0
[  180.766193] xhci_hcd 0000:00:15.0: Cleaning up stalled endpoint ring
[  180.766195] xhci_hcd 0000:00:15.0: Finding endpoint context
[  180.766197] xhci_hcd 0000:00:15.0: Cycle state = 0x1
[  180.766200] xhci_hcd 0000:00:15.0: New dequeue segment = 0000000077472ecb (virtual)
[  180.766202] xhci_hcd 0000:00:15.0: New dequeue pointer = 0xfffbb380 (DMA)
[  180.766203] xhci_hcd 0000:00:15.0: Queueing new dequeue state
[  180.766206] xhci_hcd 0000:00:15.0: Set TR Deq Ptr cmd, new deq seg = 0000000077472ecb (0xfffbb000 dma), new deq ptr = 000000009adaa385 (0xfffbb380 dma), new cycle = 1
[  180.766208] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.766214] xhci_hcd 0000:00:15.0: Giveback URB 0000000022eaaa6b, len = 0, expected = 2, status = -32
[  180.766219] xhci_hcd 0000:00:15.0: Ignoring reset ep completion code of 1
[  180.766223] xhci_hcd 0000:00:15.0: Successful Set TR Deq Ptr cmd, deq = @fffbb380
[  180.766285] xhci_hcd 0000:00:15.0: Stalled endpoint for slot 6 ep 0
[  180.766288] xhci_hcd 0000:00:15.0: Cleaning up stalled endpoint ring
[  180.766289] xhci_hcd 0000:00:15.0: Finding endpoint context
[  180.766291] xhci_hcd 0000:00:15.0: Cycle state = 0x1
[  180.766293] xhci_hcd 0000:00:15.0: New dequeue segment = 0000000077472ecb (virtual)
[  180.766294] xhci_hcd 0000:00:15.0: New dequeue pointer = 0xfffbb3b0 (DMA)
[  180.766296] xhci_hcd 0000:00:15.0: Queueing new dequeue state
[  180.766298] xhci_hcd 0000:00:15.0: Set TR Deq Ptr cmd, new deq seg = 0000000077472ecb (0xfffbb000 dma), new deq ptr = 00000000725bf079 (0xfffbb3b0 dma), new cycle = 1
[  180.766300] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.766303] xhci_hcd 0000:00:15.0: Giveback URB 0000000022eaaa6b, len = 0, expected = 2, status = -32
[  180.766308] xhci_hcd 0000:00:15.0: Ignoring reset ep completion code of 1
[  180.766310] xhci_hcd 0000:00:15.0: Successful Set TR Deq Ptr cmd, deq = @fffbb3b0
[  180.766371] xhci_hcd 0000:00:15.0: Stalled endpoint for slot 6 ep 0
[  180.766374] xhci_hcd 0000:00:15.0: Cleaning up stalled endpoint ring
[  180.766376] xhci_hcd 0000:00:15.0: Finding endpoint context
[  180.766377] xhci_hcd 0000:00:15.0: Cycle state = 0x1
[  180.766379] xhci_hcd 0000:00:15.0: New dequeue segment = 0000000077472ecb (virtual)
[  180.766381] xhci_hcd 0000:00:15.0: New dequeue pointer = 0xfffbb3e0 (DMA)
[  180.766382] xhci_hcd 0000:00:15.0: Queueing new dequeue state
[  180.766385] xhci_hcd 0000:00:15.0: Set TR Deq Ptr cmd, new deq seg = 0000000077472ecb (0xfffbb000 dma), new deq ptr = 00000000b280ea48 (0xfffbb3e0 dma), new cycle = 1
[  180.766386] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.766390] xhci_hcd 0000:00:15.0: Giveback URB 0000000022eaaa6b, len = 0, expected = 2, status = -32
[  180.766394] xhci_hcd 0000:00:15.0: Ignoring reset ep completion code of 1
[  180.766396] xhci_hcd 0000:00:15.0: Successful Set TR Deq Ptr cmd, deq = @fffbb3e0
[  180.766458] xhci_hcd 0000:00:15.0: Stalled endpoint for slot 6 ep 0
[  180.766461] xhci_hcd 0000:00:15.0: Cleaning up stalled endpoint ring
[  180.766463] xhci_hcd 0000:00:15.0: Finding endpoint context
[  180.766464] xhci_hcd 0000:00:15.0: Cycle state = 0x1
[  180.766466] xhci_hcd 0000:00:15.0: New dequeue segment = 0000000077472ecb (virtual)
[  180.766468] xhci_hcd 0000:00:15.0: New dequeue pointer = 0xfffbb410 (DMA)
[  180.766469] xhci_hcd 0000:00:15.0: Queueing new dequeue state
[  180.766471] xhci_hcd 0000:00:15.0: Set TR Deq Ptr cmd, new deq seg = 0000000077472ecb (0xfffbb000 dma), new deq ptr = 00000000f1225ad6 (0xfffbb410 dma), new cycle = 1
[  180.766473] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.766476] xhci_hcd 0000:00:15.0: Giveback URB 0000000022eaaa6b, len = 0, expected = 2, status = -32
[  180.766480] xhci_hcd 0000:00:15.0: Ignoring reset ep completion code of 1
[  180.766483] xhci_hcd 0000:00:15.0: Successful Set TR Deq Ptr cmd, deq = @fffbb410
[  180.766547] xhci_hcd 0000:00:15.0: Stalled endpoint for slot 6 ep 0
[  180.766550] xhci_hcd 0000:00:15.0: Cleaning up stalled endpoint ring
[  180.766552] xhci_hcd 0000:00:15.0: Finding endpoint context
[  180.766553] xhci_hcd 0000:00:15.0: Cycle state = 0x1
[  180.766555] xhci_hcd 0000:00:15.0: New dequeue segment = 0000000077472ecb (virtual)
[  180.766557] xhci_hcd 0000:00:15.0: New dequeue pointer = 0xfffbb440 (DMA)
[  180.766558] xhci_hcd 0000:00:15.0: Queueing new dequeue state
[  180.766560] xhci_hcd 0000:00:15.0: Set TR Deq Ptr cmd, new deq seg = 0000000077472ecb (0xfffbb000 dma), new deq ptr = 00000000d635b97f (0xfffbb440 dma), new cycle = 1
[  180.766562] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.766565] xhci_hcd 0000:00:15.0: Giveback URB 0000000022eaaa6b, len = 0, expected = 2, status = -32
[  180.766569] xhci_hcd 0000:00:15.0: Ignoring reset ep completion code of 1
[  180.766572] xhci_hcd 0000:00:15.0: Successful Set TR Deq Ptr cmd, deq = @fffbb440
[  180.766633] xhci_hcd 0000:00:15.0: Stalled endpoint for slot 6 ep 0
[  180.766636] xhci_hcd 0000:00:15.0: Cleaning up stalled endpoint ring
[  180.766638] xhci_hcd 0000:00:15.0: Finding endpoint context
[  180.766639] xhci_hcd 0000:00:15.0: Cycle state = 0x1
[  180.766641] xhci_hcd 0000:00:15.0: New dequeue segment = 0000000077472ecb (virtual)
[  180.766643] xhci_hcd 0000:00:15.0: New dequeue pointer = 0xfffbb470 (DMA)
[  180.766644] xhci_hcd 0000:00:15.0: Queueing new dequeue state
[  180.766647] xhci_hcd 0000:00:15.0: Set TR Deq Ptr cmd, new deq seg = 0000000077472ecb (0xfffbb000 dma), new deq ptr = 00000000d5687222 (0xfffbb470 dma), new cycle = 1
[  180.766648] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.766651] xhci_hcd 0000:00:15.0: Giveback URB 0000000022eaaa6b, len = 0, expected = 2, status = -32
[  180.766656] xhci_hcd 0000:00:15.0: Ignoring reset ep completion code of 1
[  180.766659] xhci_hcd 0000:00:15.0: Successful Set TR Deq Ptr cmd, deq = @fffbb470
[  180.766720] xhci_hcd 0000:00:15.0: Stalled endpoint for slot 6 ep 0
[  180.766723] xhci_hcd 0000:00:15.0: Cleaning up stalled endpoint ring
[  180.766727] xhci_hcd 0000:00:15.0: Finding endpoint context
[  180.766729] xhci_hcd 0000:00:15.0: Cycle state = 0x1
[  180.766730] xhci_hcd 0000:00:15.0: New dequeue segment = 0000000077472ecb (virtual)
[  180.766732] xhci_hcd 0000:00:15.0: New dequeue pointer = 0xfffbb4a0 (DMA)
[  180.766734] xhci_hcd 0000:00:15.0: Queueing new dequeue state
[  180.766736] xhci_hcd 0000:00:15.0: Set TR Deq Ptr cmd, new deq seg = 0000000077472ecb (0xfffbb000 dma), new deq ptr = 000000000bfdb96a (0xfffbb4a0 dma), new cycle = 1
[  180.766738] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.766741] xhci_hcd 0000:00:15.0: Giveback URB 0000000022eaaa6b, len = 0, expected = 2, status = -32
[  180.766745] xhci_hcd 0000:00:15.0: Ignoring reset ep completion code of 1
[  180.766748] xhci_hcd 0000:00:15.0: Successful Set TR Deq Ptr cmd, deq = @fffbb4a0
[  180.766809] xhci_hcd 0000:00:15.0: Stalled endpoint for slot 6 ep 0
[  180.766811] xhci_hcd 0000:00:15.0: Cleaning up stalled endpoint ring
[  180.766813] xhci_hcd 0000:00:15.0: Finding endpoint context
[  180.766814] xhci_hcd 0000:00:15.0: Cycle state = 0x1
[  180.766816] xhci_hcd 0000:00:15.0: New dequeue segment = 0000000077472ecb (virtual)
[  180.766818] xhci_hcd 0000:00:15.0: New dequeue pointer = 0xfffbb4d0 (DMA)
[  180.766819] xhci_hcd 0000:00:15.0: Queueing new dequeue state
[  180.766822] xhci_hcd 0000:00:15.0: Set TR Deq Ptr cmd, new deq seg = 0000000077472ecb (0xfffbb000 dma), new deq ptr = 000000008f1d8e65 (0xfffbb4d0 dma), new cycle = 1
[  180.766823] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.766827] xhci_hcd 0000:00:15.0: Giveback URB 0000000022eaaa6b, len = 0, expected = 2, status = -32
[  180.766831] xhci_hcd 0000:00:15.0: Ignoring reset ep completion code of 1
[  180.766833] xhci_hcd 0000:00:15.0: Successful Set TR Deq Ptr cmd, deq = @fffbb4d0
[  180.766897] xhci_hcd 0000:00:15.0: Stalled endpoint for slot 6 ep 0
[  180.766900] xhci_hcd 0000:00:15.0: Cleaning up stalled endpoint ring
[  180.766902] xhci_hcd 0000:00:15.0: Finding endpoint context
[  180.766903] xhci_hcd 0000:00:15.0: Cycle state = 0x1
[  180.766905] xhci_hcd 0000:00:15.0: New dequeue segment = 0000000077472ecb (virtual)
[  180.766907] xhci_hcd 0000:00:15.0: New dequeue pointer = 0xfffbb500 (DMA)
[  180.766908] xhci_hcd 0000:00:15.0: Queueing new dequeue state
[  180.766911] xhci_hcd 0000:00:15.0: Set TR Deq Ptr cmd, new deq seg = 0000000077472ecb (0xfffbb000 dma), new deq ptr = 0000000051eb1872 (0xfffbb500 dma), new cycle = 1
[  180.766912] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.766916] xhci_hcd 0000:00:15.0: Giveback URB 0000000022eaaa6b, len = 0, expected = 2, status = -32
[  180.766920] xhci_hcd 0000:00:15.0: Ignoring reset ep completion code of 1
[  180.766923] xhci_hcd 0000:00:15.0: Successful Set TR Deq Ptr cmd, deq = @fffbb500
[  180.766984] xhci_hcd 0000:00:15.0: Stalled endpoint for slot 6 ep 0
[  180.766987] xhci_hcd 0000:00:15.0: Cleaning up stalled endpoint ring
[  180.766988] xhci_hcd 0000:00:15.0: Finding endpoint context
[  180.766990] xhci_hcd 0000:00:15.0: Cycle state = 0x1
[  180.766991] xhci_hcd 0000:00:15.0: New dequeue segment = 0000000077472ecb (virtual)
[  180.766993] xhci_hcd 0000:00:15.0: New dequeue pointer = 0xfffbb530 (DMA)
[  180.766995] xhci_hcd 0000:00:15.0: Queueing new dequeue state
[  180.766997] xhci_hcd 0000:00:15.0: Set TR Deq Ptr cmd, new deq seg = 0000000077472ecb (0xfffbb000 dma), new deq ptr = 00000000dbb05458 (0xfffbb530 dma), new cycle = 1
[  180.766999] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.767002] xhci_hcd 0000:00:15.0: Giveback URB 0000000022eaaa6b, len = 0, expected = 2, status = -32
[  180.767006] xhci_hcd 0000:00:15.0: Ignoring reset ep completion code of 1
[  180.767009] xhci_hcd 0000:00:15.0: Successful Set TR Deq Ptr cmd, deq = @fffbb530
[  180.768724] xhci_hcd 0000:00:15.0: Stalled endpoint for slot 6 ep 0
[  180.768729] xhci_hcd 0000:00:15.0: Cleaning up stalled endpoint ring
[  180.768731] xhci_hcd 0000:00:15.0: Finding endpoint context
[  180.768733] xhci_hcd 0000:00:15.0: Cycle state = 0x1
[  180.768735] xhci_hcd 0000:00:15.0: New dequeue segment = 0000000077472ecb (virtual)
[  180.768737] xhci_hcd 0000:00:15.0: New dequeue pointer = 0xfffbb800 (DMA)
[  180.768738] xhci_hcd 0000:00:15.0: Queueing new dequeue state
[  180.768741] xhci_hcd 0000:00:15.0: Set TR Deq Ptr cmd, new deq seg = 0000000077472ecb (0xfffbb000 dma), new deq ptr = 0000000022850bc5 (0xfffbb800 dma), new cycle = 1
[  180.768742] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.768746] xhci_hcd 0000:00:15.0: Giveback URB 000000009e53f1fb, len = 0, expected = 2, status = -32
[  180.768751] xhci_hcd 0000:00:15.0: Ignoring reset ep completion code of 1
[  180.768754] xhci_hcd 0000:00:15.0: Successful Set TR Deq Ptr cmd, deq = @fffbb800
[  180.768819] xhci_hcd 0000:00:15.0: Stalled endpoint for slot 6 ep 0
[  180.768822] xhci_hcd 0000:00:15.0: Cleaning up stalled endpoint ring
[  180.768824] xhci_hcd 0000:00:15.0: Finding endpoint context
[  180.768826] xhci_hcd 0000:00:15.0: Cycle state = 0x1
[  180.768827] xhci_hcd 0000:00:15.0: New dequeue segment = 0000000077472ecb (virtual)
[  180.768829] xhci_hcd 0000:00:15.0: New dequeue pointer = 0xfffbb830 (DMA)
[  180.768831] xhci_hcd 0000:00:15.0: Queueing new dequeue state
[  180.768833] xhci_hcd 0000:00:15.0: Set TR Deq Ptr cmd, new deq seg = 0000000077472ecb (0xfffbb000 dma), new deq ptr = 0000000011c01fba (0xfffbb830 dma), new cycle = 1
[  180.768835] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.768838] xhci_hcd 0000:00:15.0: Giveback URB 000000009e53f1fb, len = 0, expected = 2, status = -32
[  180.768842] xhci_hcd 0000:00:15.0: Ignoring reset ep completion code of 1
[  180.768845] xhci_hcd 0000:00:15.0: Successful Set TR Deq Ptr cmd, deq = @fffbb830
[  180.768907] xhci_hcd 0000:00:15.0: Stalled endpoint for slot 6 ep 0
[  180.768910] xhci_hcd 0000:00:15.0: Cleaning up stalled endpoint ring
[  180.768911] xhci_hcd 0000:00:15.0: Finding endpoint context
[  180.768913] xhci_hcd 0000:00:15.0: Cycle state = 0x1
[  180.768915] xhci_hcd 0000:00:15.0: New dequeue segment = 0000000077472ecb (virtual)
[  180.768916] xhci_hcd 0000:00:15.0: New dequeue pointer = 0xfffbb860 (DMA)
[  180.768918] xhci_hcd 0000:00:15.0: Queueing new dequeue state
[  180.768920] xhci_hcd 0000:00:15.0: Set TR Deq Ptr cmd, new deq seg = 0000000077472ecb (0xfffbb000 dma), new deq ptr = 0000000009f9a97b (0xfffbb860 dma), new cycle = 1
[  180.768922] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.768925] xhci_hcd 0000:00:15.0: Giveback URB 000000009e53f1fb, len = 0, expected = 2, status = -32
[  180.768929] xhci_hcd 0000:00:15.0: Ignoring reset ep completion code of 1
[  180.768932] xhci_hcd 0000:00:15.0: Successful Set TR Deq Ptr cmd, deq = @fffbb860
[  180.768993] xhci_hcd 0000:00:15.0: Stalled endpoint for slot 6 ep 0
[  180.768996] xhci_hcd 0000:00:15.0: Cleaning up stalled endpoint ring
[  180.768998] xhci_hcd 0000:00:15.0: Finding endpoint context
[  180.769000] xhci_hcd 0000:00:15.0: Cycle state = 0x1
[  180.769001] xhci_hcd 0000:00:15.0: New dequeue segment = 0000000077472ecb (virtual)
[  180.769003] xhci_hcd 0000:00:15.0: New dequeue pointer = 0xfffbb890 (DMA)
[  180.769004] xhci_hcd 0000:00:15.0: Queueing new dequeue state
[  180.769007] xhci_hcd 0000:00:15.0: Set TR Deq Ptr cmd, new deq seg = 0000000077472ecb (0xfffbb000 dma), new deq ptr = 00000000755eb35e (0xfffbb890 dma), new cycle = 1
[  180.769008] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.769012] xhci_hcd 0000:00:15.0: Giveback URB 000000009e53f1fb, len = 0, expected = 2, status = -32
[  180.769016] xhci_hcd 0000:00:15.0: Ignoring reset ep completion code of 1
[  180.769019] xhci_hcd 0000:00:15.0: Successful Set TR Deq Ptr cmd, deq = @fffbb890
[  180.769080] xhci_hcd 0000:00:15.0: Stalled endpoint for slot 6 ep 0
[  180.769083] xhci_hcd 0000:00:15.0: Cleaning up stalled endpoint ring
[  180.769085] xhci_hcd 0000:00:15.0: Finding endpoint context
[  180.769086] xhci_hcd 0000:00:15.0: Cycle state = 0x1
[  180.769088] xhci_hcd 0000:00:15.0: New dequeue segment = 0000000077472ecb (virtual)
[  180.769090] xhci_hcd 0000:00:15.0: New dequeue pointer = 0xfffbb8c0 (DMA)
[  180.769091] xhci_hcd 0000:00:15.0: Queueing new dequeue state
[  180.769094] xhci_hcd 0000:00:15.0: Set TR Deq Ptr cmd, new deq seg = 0000000077472ecb (0xfffbb000 dma), new deq ptr = 00000000b7e9dd6e (0xfffbb8c0 dma), new cycle = 1
[  180.769095] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.769098] xhci_hcd 0000:00:15.0: Giveback URB 000000009e53f1fb, len = 0, expected = 2, status = -32
[  180.769103] xhci_hcd 0000:00:15.0: Ignoring reset ep completion code of 1
[  180.769105] xhci_hcd 0000:00:15.0: Successful Set TR Deq Ptr cmd, deq = @fffbb8c0
[  180.769172] xhci_hcd 0000:00:15.0: Stalled endpoint for slot 6 ep 0
[  180.769175] xhci_hcd 0000:00:15.0: Cleaning up stalled endpoint ring
[  180.769177] xhci_hcd 0000:00:15.0: Finding endpoint context
[  180.769179] xhci_hcd 0000:00:15.0: Cycle state = 0x1
[  180.769180] xhci_hcd 0000:00:15.0: New dequeue segment = 0000000077472ecb (virtual)
[  180.769182] xhci_hcd 0000:00:15.0: New dequeue pointer = 0xfffbb8f0 (DMA)
[  180.769184] xhci_hcd 0000:00:15.0: Queueing new dequeue state
[  180.769186] xhci_hcd 0000:00:15.0: Set TR Deq Ptr cmd, new deq seg = 0000000077472ecb (0xfffbb000 dma), new deq ptr = 000000000e9deab8 (0xfffbb8f0 dma), new cycle = 1
[  180.769188] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.769191] xhci_hcd 0000:00:15.0: Giveback URB 000000009e53f1fb, len = 0, expected = 2, status = -32
[  180.769195] xhci_hcd 0000:00:15.0: Ignoring reset ep completion code of 1
[  180.769198] xhci_hcd 0000:00:15.0: Successful Set TR Deq Ptr cmd, deq = @fffbb8f0
[  180.769259] xhci_hcd 0000:00:15.0: Stalled endpoint for slot 6 ep 0
[  180.769262] xhci_hcd 0000:00:15.0: Cleaning up stalled endpoint ring
[  180.769264] xhci_hcd 0000:00:15.0: Finding endpoint context
[  180.769265] xhci_hcd 0000:00:15.0: Cycle state = 0x1
[  180.769267] xhci_hcd 0000:00:15.0: New dequeue segment = 0000000077472ecb (virtual)
[  180.769269] xhci_hcd 0000:00:15.0: New dequeue pointer = 0xfffbb920 (DMA)
[  180.769270] xhci_hcd 0000:00:15.0: Queueing new dequeue state
[  180.769273] xhci_hcd 0000:00:15.0: Set TR Deq Ptr cmd, new deq seg = 0000000077472ecb (0xfffbb000 dma), new deq ptr = 00000000cd35f113 (0xfffbb920 dma), new cycle = 1
[  180.769274] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.769278] xhci_hcd 0000:00:15.0: Giveback URB 000000009e53f1fb, len = 0, expected = 2, status = -32
[  180.769282] xhci_hcd 0000:00:15.0: Ignoring reset ep completion code of 1
[  180.769284] xhci_hcd 0000:00:15.0: Successful Set TR Deq Ptr cmd, deq = @fffbb920
[  180.769346] xhci_hcd 0000:00:15.0: Stalled endpoint for slot 6 ep 0
[  180.769349] xhci_hcd 0000:00:15.0: Cleaning up stalled endpoint ring
[  180.769350] xhci_hcd 0000:00:15.0: Finding endpoint context
[  180.769352] xhci_hcd 0000:00:15.0: Cycle state = 0x1
[  180.769354] xhci_hcd 0000:00:15.0: New dequeue segment = 0000000077472ecb (virtual)
[  180.769355] xhci_hcd 0000:00:15.0: New dequeue pointer = 0xfffbb950 (DMA)
[  180.769357] xhci_hcd 0000:00:15.0: Queueing new dequeue state
[  180.769359] xhci_hcd 0000:00:15.0: Set TR Deq Ptr cmd, new deq seg = 0000000077472ecb (0xfffbb000 dma), new deq ptr = 000000004e2b02c1 (0xfffbb950 dma), new cycle = 1
[  180.769361] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.769364] xhci_hcd 0000:00:15.0: Giveback URB 000000009e53f1fb, len = 0, expected = 2, status = -32
[  180.769368] xhci_hcd 0000:00:15.0: Ignoring reset ep completion code of 1
[  180.769371] xhci_hcd 0000:00:15.0: Successful Set TR Deq Ptr cmd, deq = @fffbb950
[  180.769432] xhci_hcd 0000:00:15.0: Stalled endpoint for slot 6 ep 0
[  180.769436] xhci_hcd 0000:00:15.0: Cleaning up stalled endpoint ring
[  180.769437] xhci_hcd 0000:00:15.0: Finding endpoint context
[  180.769439] xhci_hcd 0000:00:15.0: Cycle state = 0x1
[  180.769440] xhci_hcd 0000:00:15.0: New dequeue segment = 0000000077472ecb (virtual)
[  180.769442] xhci_hcd 0000:00:15.0: New dequeue pointer = 0xfffbb980 (DMA)
[  180.769444] xhci_hcd 0000:00:15.0: Queueing new dequeue state
[  180.769446] xhci_hcd 0000:00:15.0: Set TR Deq Ptr cmd, new deq seg = 0000000077472ecb (0xfffbb000 dma), new deq ptr = 0000000008ea345f (0xfffbb980 dma), new cycle = 1
[  180.769448] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.769451] xhci_hcd 0000:00:15.0: Giveback URB 000000009e53f1fb, len = 0, expected = 2, status = -32
[  180.769455] xhci_hcd 0000:00:15.0: Ignoring reset ep completion code of 1
[  180.769458] xhci_hcd 0000:00:15.0: Successful Set TR Deq Ptr cmd, deq = @fffbb980
[  180.769522] xhci_hcd 0000:00:15.0: Stalled endpoint for slot 6 ep 0
[  180.769525] xhci_hcd 0000:00:15.0: Cleaning up stalled endpoint ring
[  180.769527] xhci_hcd 0000:00:15.0: Finding endpoint context
[  180.769529] xhci_hcd 0000:00:15.0: Cycle state = 0x1
[  180.769530] xhci_hcd 0000:00:15.0: New dequeue segment = 0000000077472ecb (virtual)
[  180.769532] xhci_hcd 0000:00:15.0: New dequeue pointer = 0xfffbb9b0 (DMA)
[  180.769533] xhci_hcd 0000:00:15.0: Queueing new dequeue state
[  180.769536] xhci_hcd 0000:00:15.0: Set TR Deq Ptr cmd, new deq seg = 0000000077472ecb (0xfffbb000 dma), new deq ptr = 0000000066770bf1 (0xfffbb9b0 dma), new cycle = 1
[  180.769537] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.769541] xhci_hcd 0000:00:15.0: Giveback URB 000000009e53f1fb, len = 0, expected = 2, status = -32
[  180.769545] xhci_hcd 0000:00:15.0: Ignoring reset ep completion code of 1
[  180.769547] xhci_hcd 0000:00:15.0: Successful Set TR Deq Ptr cmd, deq = @fffbb9b0
[  180.770321] xhci_hcd 0000:00:15.0: Stalled endpoint for slot 6 ep 0
[  180.770324] xhci_hcd 0000:00:15.0: Cleaning up stalled endpoint ring
[  180.770326] xhci_hcd 0000:00:15.0: Finding endpoint context
[  180.770327] xhci_hcd 0000:00:15.0: Cycle state = 0x1
[  180.770329] xhci_hcd 0000:00:15.0: New dequeue segment = 0000000077472ecb (virtual)
[  180.770331] xhci_hcd 0000:00:15.0: New dequeue pointer = 0xfffbbb60 (DMA)
[  180.770332] xhci_hcd 0000:00:15.0: Queueing new dequeue state
[  180.770335] xhci_hcd 0000:00:15.0: Set TR Deq Ptr cmd, new deq seg = 0000000077472ecb (0xfffbb000 dma), new deq ptr = 000000001bf17731 (0xfffbbb60 dma), new cycle = 1
[  180.770337] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.770340] xhci_hcd 0000:00:15.0: Giveback URB 00000000372f0b9b, len = 0, expected = 2, status = -32
[  180.770344] xhci_hcd 0000:00:15.0: Ignoring reset ep completion code of 1
[  180.770346] xhci_hcd 0000:00:15.0: Successful Set TR Deq Ptr cmd, deq = @fffbbb60
[  180.770408] xhci_hcd 0000:00:15.0: Stalled endpoint for slot 6 ep 0
[  180.770411] xhci_hcd 0000:00:15.0: Cleaning up stalled endpoint ring
[  180.770412] xhci_hcd 0000:00:15.0: Finding endpoint context
[  180.770414] xhci_hcd 0000:00:15.0: Cycle state = 0x1
[  180.770416] xhci_hcd 0000:00:15.0: New dequeue segment = 0000000077472ecb (virtual)
[  180.770417] xhci_hcd 0000:00:15.0: New dequeue pointer = 0xfffbbb90 (DMA)
[  180.770419] xhci_hcd 0000:00:15.0: Queueing new dequeue state
[  180.770421] xhci_hcd 0000:00:15.0: Set TR Deq Ptr cmd, new deq seg = 0000000077472ecb (0xfffbb000 dma), new deq ptr = 00000000a7e40844 (0xfffbbb90 dma), new cycle = 1
[  180.770423] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.770426] xhci_hcd 0000:00:15.0: Giveback URB 00000000372f0b9b, len = 0, expected = 2, status = -32
[  180.770430] xhci_hcd 0000:00:15.0: Ignoring reset ep completion code of 1
[  180.770433] xhci_hcd 0000:00:15.0: Successful Set TR Deq Ptr cmd, deq = @fffbbb90
[  180.770495] xhci_hcd 0000:00:15.0: Stalled endpoint for slot 6 ep 0
[  180.770498] xhci_hcd 0000:00:15.0: Cleaning up stalled endpoint ring
[  180.770499] xhci_hcd 0000:00:15.0: Finding endpoint context
[  180.770501] xhci_hcd 0000:00:15.0: Cycle state = 0x1
[  180.770503] xhci_hcd 0000:00:15.0: New dequeue segment = 0000000077472ecb (virtual)
[  180.770504] xhci_hcd 0000:00:15.0: New dequeue pointer = 0xfffbbbc0 (DMA)
[  180.770506] xhci_hcd 0000:00:15.0: Queueing new dequeue state
[  180.770508] xhci_hcd 0000:00:15.0: Set TR Deq Ptr cmd, new deq seg = 0000000077472ecb (0xfffbb000 dma), new deq ptr = 000000008e15a159 (0xfffbbbc0 dma), new cycle = 1
[  180.770510] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.770513] xhci_hcd 0000:00:15.0: Giveback URB 00000000372f0b9b, len = 0, expected = 2, status = -32
[  180.770517] xhci_hcd 0000:00:15.0: Ignoring reset ep completion code of 1
[  180.770520] xhci_hcd 0000:00:15.0: Successful Set TR Deq Ptr cmd, deq = @fffbbbc0
[  180.770581] xhci_hcd 0000:00:15.0: Stalled endpoint for slot 6 ep 0
[  180.770584] xhci_hcd 0000:00:15.0: Cleaning up stalled endpoint ring
[  180.770585] xhci_hcd 0000:00:15.0: Finding endpoint context
[  180.770587] xhci_hcd 0000:00:15.0: Cycle state = 0x1
[  180.770589] xhci_hcd 0000:00:15.0: New dequeue segment = 0000000077472ecb (virtual)
[  180.770590] xhci_hcd 0000:00:15.0: New dequeue pointer = 0xfffbbbf0 (DMA)
[  180.770592] xhci_hcd 0000:00:15.0: Queueing new dequeue state
[  180.770594] xhci_hcd 0000:00:15.0: Set TR Deq Ptr cmd, new deq seg = 0000000077472ecb (0xfffbb000 dma), new deq ptr = 00000000942ca8a8 (0xfffbbbf0 dma), new cycle = 1
[  180.770596] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.770599] xhci_hcd 0000:00:15.0: Giveback URB 00000000372f0b9b, len = 0, expected = 2, status = -32
[  180.770603] xhci_hcd 0000:00:15.0: Ignoring reset ep completion code of 1
[  180.770606] xhci_hcd 0000:00:15.0: Successful Set TR Deq Ptr cmd, deq = @fffbbbf0
[  180.770672] xhci_hcd 0000:00:15.0: Stalled endpoint for slot 6 ep 0
[  180.770675] xhci_hcd 0000:00:15.0: Cleaning up stalled endpoint ring
[  180.770677] xhci_hcd 0000:00:15.0: Finding endpoint context
[  180.770678] xhci_hcd 0000:00:15.0: Cycle state = 0x1
[  180.770680] xhci_hcd 0000:00:15.0: New dequeue segment = 0000000077472ecb (virtual)
[  180.770682] xhci_hcd 0000:00:15.0: New dequeue pointer = 0xfffbbc20 (DMA)
[  180.770683] xhci_hcd 0000:00:15.0: Queueing new dequeue state
[  180.770686] xhci_hcd 0000:00:15.0: Set TR Deq Ptr cmd, new deq seg = 0000000077472ecb (0xfffbb000 dma), new deq ptr = 000000008675ce12 (0xfffbbc20 dma), new cycle = 1
[  180.770687] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.770691] xhci_hcd 0000:00:15.0: Giveback URB 00000000372f0b9b, len = 0, expected = 2, status = -32
[  180.770695] xhci_hcd 0000:00:15.0: Ignoring reset ep completion code of 1
[  180.770698] xhci_hcd 0000:00:15.0: Successful Set TR Deq Ptr cmd, deq = @fffbbc20
[  180.770759] xhci_hcd 0000:00:15.0: Stalled endpoint for slot 6 ep 0
[  180.770762] xhci_hcd 0000:00:15.0: Cleaning up stalled endpoint ring
[  180.770764] xhci_hcd 0000:00:15.0: Finding endpoint context
[  180.770765] xhci_hcd 0000:00:15.0: Cycle state = 0x1
[  180.770767] xhci_hcd 0000:00:15.0: New dequeue segment = 0000000077472ecb (virtual)
[  180.770769] xhci_hcd 0000:00:15.0: New dequeue pointer = 0xfffbbc50 (DMA)
[  180.770770] xhci_hcd 0000:00:15.0: Queueing new dequeue state
[  180.770772] xhci_hcd 0000:00:15.0: Set TR Deq Ptr cmd, new deq seg = 0000000077472ecb (0xfffbb000 dma), new deq ptr = 000000002cf2c3aa (0xfffbbc50 dma), new cycle = 1
[  180.770774] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.770777] xhci_hcd 0000:00:15.0: Giveback URB 00000000372f0b9b, len = 0, expected = 2, status = -32
[  180.770781] xhci_hcd 0000:00:15.0: Ignoring reset ep completion code of 1
[  180.770784] xhci_hcd 0000:00:15.0: Successful Set TR Deq Ptr cmd, deq = @fffbbc50
[  180.770845] xhci_hcd 0000:00:15.0: Stalled endpoint for slot 6 ep 0
[  180.770848] xhci_hcd 0000:00:15.0: Cleaning up stalled endpoint ring
[  180.770850] xhci_hcd 0000:00:15.0: Finding endpoint context
[  180.770851] xhci_hcd 0000:00:15.0: Cycle state = 0x1
[  180.770853] xhci_hcd 0000:00:15.0: New dequeue segment = 0000000077472ecb (virtual)
[  180.770855] xhci_hcd 0000:00:15.0: New dequeue pointer = 0xfffbbc80 (DMA)
[  180.770856] xhci_hcd 0000:00:15.0: Queueing new dequeue state
[  180.770859] xhci_hcd 0000:00:15.0: Set TR Deq Ptr cmd, new deq seg = 0000000077472ecb (0xfffbb000 dma), new deq ptr = 000000005592fbb3 (0xfffbbc80 dma), new cycle = 1
[  180.770860] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.770864] xhci_hcd 0000:00:15.0: Giveback URB 00000000372f0b9b, len = 0, expected = 2, status = -32
[  180.770868] xhci_hcd 0000:00:15.0: Ignoring reset ep completion code of 1
[  180.770870] xhci_hcd 0000:00:15.0: Successful Set TR Deq Ptr cmd, deq = @fffbbc80
[  180.770932] xhci_hcd 0000:00:15.0: Stalled endpoint for slot 6 ep 0
[  180.770934] xhci_hcd 0000:00:15.0: Cleaning up stalled endpoint ring
[  180.770936] xhci_hcd 0000:00:15.0: Finding endpoint context
[  180.770938] xhci_hcd 0000:00:15.0: Cycle state = 0x1
[  180.770939] xhci_hcd 0000:00:15.0: New dequeue segment = 0000000077472ecb (virtual)
[  180.770941] xhci_hcd 0000:00:15.0: New dequeue pointer = 0xfffbbcb0 (DMA)
[  180.770943] xhci_hcd 0000:00:15.0: Queueing new dequeue state
[  180.770945] xhci_hcd 0000:00:15.0: Set TR Deq Ptr cmd, new deq seg = 0000000077472ecb (0xfffbb000 dma), new deq ptr = 00000000b0f6b47d (0xfffbbcb0 dma), new cycle = 1
[  180.770947] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.770950] xhci_hcd 0000:00:15.0: Giveback URB 00000000372f0b9b, len = 0, expected = 2, status = -32
[  180.770954] xhci_hcd 0000:00:15.0: Ignoring reset ep completion code of 1
[  180.770957] xhci_hcd 0000:00:15.0: Successful Set TR Deq Ptr cmd, deq = @fffbbcb0
[  180.771023] xhci_hcd 0000:00:15.0: Stalled endpoint for slot 6 ep 0
[  180.771026] xhci_hcd 0000:00:15.0: Cleaning up stalled endpoint ring
[  180.771027] xhci_hcd 0000:00:15.0: Finding endpoint context
[  180.771029] xhci_hcd 0000:00:15.0: Cycle state = 0x1
[  180.771031] xhci_hcd 0000:00:15.0: New dequeue segment = 0000000077472ecb (virtual)
[  180.771033] xhci_hcd 0000:00:15.0: New dequeue pointer = 0xfffbbce0 (DMA)
[  180.771034] xhci_hcd 0000:00:15.0: Queueing new dequeue state
[  180.771036] xhci_hcd 0000:00:15.0: Set TR Deq Ptr cmd, new deq seg = 0000000077472ecb (0xfffbb000 dma), new deq ptr = 000000000e92a6ea (0xfffbbce0 dma), new cycle = 1
[  180.771038] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.771041] xhci_hcd 0000:00:15.0: Giveback URB 00000000372f0b9b, len = 0, expected = 2, status = -32
[  180.771045] xhci_hcd 0000:00:15.0: Ignoring reset ep completion code of 1
[  180.771048] xhci_hcd 0000:00:15.0: Successful Set TR Deq Ptr cmd, deq = @fffbbce0
[  180.771109] xhci_hcd 0000:00:15.0: Stalled endpoint for slot 6 ep 0
[  180.771113] xhci_hcd 0000:00:15.0: Cleaning up stalled endpoint ring
[  180.771115] xhci_hcd 0000:00:15.0: Finding endpoint context
[  180.771116] xhci_hcd 0000:00:15.0: Cycle state = 0x1
[  180.771118] xhci_hcd 0000:00:15.0: New dequeue segment = 0000000077472ecb (virtual)
[  180.771120] xhci_hcd 0000:00:15.0: New dequeue pointer = 0xfffbbd10 (DMA)
[  180.771121] xhci_hcd 0000:00:15.0: Queueing new dequeue state
[  180.771123] xhci_hcd 0000:00:15.0: Set TR Deq Ptr cmd, new deq seg = 0000000077472ecb (0xfffbb000 dma), new deq ptr = 0000000018d588e2 (0xfffbbd10 dma), new cycle = 1
[  180.771125] xhci_hcd 0000:00:15.0: // Ding dong!
[  180.771128] xhci_hcd 0000:00:15.0: Giveback URB 00000000372f0b9b, len = 0, expected = 2, status = -32
[  180.771132] xhci_hcd 0000:00:15.0: Ignoring reset ep completion code of 1
[  180.771135] xhci_hcd 0000:00:15.0: Successful Set TR Deq Ptr cmd, deq = @fffbbd10
[  180.772606] usbcore: registered new interface driver snd-usb-audio
