Signed-off-by: Paul Zimmerman <[email protected]>
---
drivers/usb/dwc2/pci.c | 591 ++++++++++++++++++++++++++++++++++++++++++++++++
1 files changed, 591 insertions(+), 0 deletions(-)
create mode 100644 drivers/usb/dwc2/pci.c
diff --git a/drivers/usb/dwc2/pci.c b/drivers/usb/dwc2/pci.c
new file mode 100644
index 0000000..2aef356
--- /dev/null
+++ b/drivers/usb/dwc2/pci.c
@@ -0,0 +1,591 @@
+/*
+ * pci.c - DesignWare HS OTG Controller PCI driver
+ *
+ * Copyright (C) 2004-2012 Synopsys, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions, and the following disclaimer,
+ * without modification.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * 3. The names of the above-listed copyright holders may not be used
+ * to endorse or promote products derived from this software without
+ * specific prior written permission.
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation; either version 2 of the License, or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+ * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+ * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Provides the initialization and cleanup entry points for the DWC_otg PCI
+ * driver
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/dma-mapping.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/pci.h>
+#include <linux/usb.h>
+
+#include <linux/usb/hcd.h>
+#include <linux/usb/ch11.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/ch9.h>
+
+#include "core.h"
+#include "hcd.h"
+
+static const char driver_name[] = "dwc_otg";
+
+/*-------------------------------------------------------------------------*/
+/* Encapsulate the module parameter settings */
+
+struct dwc2_driver_module_params {
+ int otg_cap;
+ int dma_enable;
+ int dma_desc_enable;
+ int dma_burst_size;
+ int speed;
+ int host_support_fs_ls_low_power;
+ int host_ls_low_power_phy_clk;
+ int enable_dynamic_fifo;
+ int host_rx_fifo_size;
+ int host_nperio_tx_fifo_size;
+ int host_perio_tx_fifo_size;
+ int max_transfer_size;
+ int max_packet_count;
+ int host_channels;
+ int phy_type;
+ int phy_utmi_width;
+ int phy_ulpi_ddr;
+ int phy_ulpi_ext_vbus;
+ int i2c_enable;
+ int ulpi_fs_ls;
+ int ts_dline;
+ int en_multiple_tx_fifo;
+ int lpm_enable;
+ int ic_usb_cap;
+ int reload_ctl;
+ int ahb_single;
+ int otg_ver;
+};
+
+static struct dwc2_driver_module_params dwc2_module_params = {
+ .otg_cap = 0, /* HNP/SRP capable */
+ .dma_enable = 1,
+ .dma_desc_enable = 1,
+ .dma_burst_size = 32,
+ .speed = 0, /* High Speed */
+ .host_support_fs_ls_low_power = 0,
+ .host_ls_low_power_phy_clk = 0, /* 48 MHz */
+ .enable_dynamic_fifo = 1,
+ .host_rx_fifo_size = 1024, /* 1K DWORDs */
+ .host_nperio_tx_fifo_size = 256, /* 256 DWORDs */
+ .host_perio_tx_fifo_size = 1024, /* 1K DWORDs */
+ .max_transfer_size = 65535,
+ .max_packet_count = 511,
+ .host_channels = 11,
+ .phy_type = 1, /* UTMI */
+ .phy_utmi_width = 16, /* 16 bits */
+ .phy_ulpi_ddr = 0, /* Single */
+ .phy_ulpi_ext_vbus = 0,
+ .i2c_enable = 0,
+ .ulpi_fs_ls = 0,
+ .ts_dline = 0,
+ .en_multiple_tx_fifo = 1,
+ .lpm_enable = 0,
+ .ic_usb_cap = 0,
+ .reload_ctl = 0,
+ .ahb_single = 0,
+ .otg_ver = 0, /* 1.3 */
+};
+
+/*
+ * This function is called during module intialization to pass module
parameters
+ * for the DWC_otg core. It returns non-0 if any parameters are invalid.
+ */
+int dwc2_set_parameters(struct dwc2_hcd *hcd)
+{
+ int retval = 0;
+
+ dev_dbg(hcd->dev, "%s()\n", __func__);
+
+ retval |= dwc2_set_param_otg_cap(hcd, dwc2_module_params.otg_cap);
+ retval |= dwc2_set_param_dma_enable(hcd, dwc2_module_params.dma_enable);
+ retval |= dwc2_set_param_dma_desc_enable(hcd,
+ dwc2_module_params.dma_desc_enable);
+ retval |= dwc2_set_param_dma_burst_size(hcd,
+ dwc2_module_params.dma_burst_size);
+ retval |= dwc2_set_param_host_support_fs_ls_low_power(hcd,
+ dwc2_module_params.host_support_fs_ls_low_power);
+ retval |= dwc2_set_param_enable_dynamic_fifo(hcd,
+ dwc2_module_params.enable_dynamic_fifo);
+ retval |= dwc2_set_param_host_rx_fifo_size(hcd,
+ dwc2_module_params.host_rx_fifo_size);
+ retval |= dwc2_set_param_host_nperio_tx_fifo_size(hcd,
+ dwc2_module_params.host_nperio_tx_fifo_size);
+ retval |= dwc2_set_param_host_perio_tx_fifo_size(hcd,
+ dwc2_module_params.host_perio_tx_fifo_size);
+ retval |= dwc2_set_param_max_transfer_size(hcd,
+ dwc2_module_params.max_transfer_size);
+ retval |= dwc2_set_param_max_packet_count(hcd,
+ dwc2_module_params.max_packet_count);
+ retval |= dwc2_set_param_host_channels(hcd,
+ dwc2_module_params.host_channels);
+ retval |= dwc2_set_param_phy_type(hcd, dwc2_module_params.phy_type);
+ retval |= dwc2_set_param_speed(hcd, dwc2_module_params.speed);
+ retval |= dwc2_set_param_host_ls_low_power_phy_clk(hcd,
+ dwc2_module_params.host_ls_low_power_phy_clk);
+ retval |= dwc2_set_param_phy_ulpi_ddr(hcd,
+ dwc2_module_params.phy_ulpi_ddr);
+ retval |= dwc2_set_param_phy_ulpi_ext_vbus(hcd,
+ dwc2_module_params.phy_ulpi_ext_vbus);
+ retval |= dwc2_set_param_phy_utmi_width(hcd,
+ dwc2_module_params.phy_utmi_width);
+ retval |= dwc2_set_param_ulpi_fs_ls(hcd, dwc2_module_params.ulpi_fs_ls);
+ retval |= dwc2_set_param_ts_dline(hcd, dwc2_module_params.ts_dline);
+ retval |= dwc2_set_param_i2c_enable(hcd, dwc2_module_params.i2c_enable);
+ retval |= dwc2_set_param_en_multiple_tx_fifo(hcd,
+ dwc2_module_params.en_multiple_tx_fifo);
+ retval |= dwc2_set_param_lpm_enable(hcd, dwc2_module_params.lpm_enable);
+ retval |= dwc2_set_param_ic_usb_cap(hcd, dwc2_module_params.ic_usb_cap);
+ retval |= dwc2_set_param_reload_ctl(hcd, dwc2_module_params.reload_ctl);
+ retval |= dwc2_set_param_ahb_single(hcd, dwc2_module_params.ahb_single);
+ retval |= dwc2_set_param_otg_ver(hcd, dwc2_module_params.otg_ver);
+
+ return retval;
+}
+
+/*
+ * This function is the top level interrupt handler for the Common
+ * (both Device and Host mode) interrupts
+ */
+static irqreturn_t common_irq(int irq, void *dev)
+{
+ int retval = IRQ_NONE;
+
+ retval = dwc2_handle_common_intr(dev);
+ return IRQ_RETVAL(retval);
+}
+
+/**
+ * driver_remove() - Called when the DWC_otg core is unregistered with the
+ * DWC_otg driver
+ *
+ * @dev: Bus device
+ *
+ * This routine is called, for example, when the rmmod command is executed. The
+ * device may or may not be electrically present. If it is present, the driver
+ * stops device processing. Any resources used on behalf of this device are
+ * freed.
+ */
+static void driver_remove(struct pci_dev *dev)
+{
+ struct dwc2_device *otg_dev = pci_get_drvdata(dev);
+
+ dev_dbg(&dev->dev, "%s(%p)\n", __func__, dev);
+
+ if (!otg_dev) {
+ dev_dbg(&dev->dev, "%s: otg_dev NULL!\n", __func__);
+ return;
+ }
+
+ dev_dbg(&dev->dev, "otg_dev->hcd = %p\n", otg_dev->hcd);
+ if (otg_dev->hcd)
+ dwc2_hcd_remove(&dev->dev, otg_dev);
+ else
+ dev_dbg(&dev->dev, "%s: otg_dev->hcd NULL!\n", __func__);
+
+#ifndef DWC_HOST_ONLY
+ if (otg_dev->pcd)
+ dwc2_pcd_remove(&dev->dev, otg_dev);
+ else
+ dev_dbg(&dev->dev, "%s: otg_dev->pcd NULL!\n", __func__);
+#endif
+
+ /* Free the IRQ */
+ if (otg_dev->common_irq_installed) {
+ otg_dev->common_irq_installed = 0;
+ free_irq(dev->irq, otg_dev);
+ } else {
+ dev_dbg(&dev->dev, "%s: There is no installed irq!\n",
+ __func__);
+ }
+
+ /* Release the register space */
+ if (otg_dev->base)
+ iounmap(otg_dev->base);
+ release_mem_region(otg_dev->rsrc_start, otg_dev->rsrc_len);
+
+ /* Return the memory */
+ kfree(otg_dev);
+
+ /* Clear the drvdata pointer */
+ pci_set_drvdata(dev, 0);
+}
+
+/**
+ * driver_probe() - Called when the DWC_otg core is bound to the DWC_otg driver
+ *
+ * @dev: Bus device
+ *
+ * This routine creates the driver components required to control the device
+ * (core, HCD, and PCD) and initializes the device. The driver components are
+ * stored in a dwc2_device structure. A reference to the dwc2_device is saved
+ * in the device private data. This allows the driver to access the dwc2_device
+ * structure on subsequent calls to driver methods for this device.
+ */
+static int driver_probe(struct pci_dev *dev, const struct pci_device_id *id)
+{
+ struct dwc2_device *otg_dev;
+ int retval;
+
+ dev_dbg(&dev->dev, "driver_probe(%p)\n", dev);
+
+ if (!id) {
+ dev_err(&dev->dev, "Invalid pci_device_id %p", id);
+ return -EINVAL;
+ }
+
+ if (!dev || pci_enable_device(dev) < 0) {
+ dev_err(&dev->dev, "Invalid pci_device %p", dev);
+ return -ENODEV;
+ }
+ dev_dbg(&dev->dev, "start=0x%08x\n",
+ (unsigned)pci_resource_start(dev, 0));
+ /* other stuff needed as well? */
+
+ otg_dev = kzalloc(sizeof(*otg_dev), GFP_KERNEL);
+ if (!otg_dev) {
+ dev_err(&dev->dev, "kzalloc of otg_dev failed\n");
+ return -ENOMEM;
+ }
+
+ /* Map the DWC_otg Core memory into virtual address space */
+ dev->current_state = PCI_D0;
+ dev->dev.power.power_state = PMSG_ON;
+
+ if (!dev->irq) {
+ dev_err(&dev->dev,
+ "Found HC with no IRQ. Check BIOS/PCI %s setup!",
+ pci_name(dev));
+ retval = -ENODEV;
+ goto fail1;
+ }
+
+ otg_dev->rsrc_start = pci_resource_start(dev, 0);
+ otg_dev->rsrc_len = pci_resource_len(dev, 0);
+ dev_dbg(&dev->dev, "PCI resource: start=%08x, len=%08x\n",
+ (unsigned)otg_dev->rsrc_start,
+ (unsigned)otg_dev->rsrc_len);
+ if (!request_mem_region(otg_dev->rsrc_start,
+ otg_dev->rsrc_len, "dwc_otg")) {
+ dev_dbg(&dev->dev, "error requesting register space\n");
+ retval = -ENOMEM;
+ goto fail1;
+ }
+
+ otg_dev->base = ioremap_nocache(otg_dev->rsrc_start,
+ otg_dev->rsrc_len);
+ if (otg_dev->base == NULL) {
+ dev_dbg(&dev->dev, "error mapping registers\n");
+ retval = -ENOMEM;
+ goto fail2;
+ }
+ dev_dbg(&dev->dev, "base=0x%p\n", otg_dev->base);
+ dev_dbg(&dev->dev, "%s: mapped PA %1x to VA %p\n", __func__,
+ (unsigned)otg_dev->rsrc_start,
+ otg_dev->base);
+
+ pci_set_master(dev);
+
+ /*
+ * Initialize driver data to point to the global DWC_otg Device
+ * structure
+ */
+ pci_set_drvdata(dev, otg_dev);
+ dev_dbg(&dev->dev, "otg_dev=0x%p\n", otg_dev);
+
+ /*
+ * Attempt to ensure this device is really a DWC_otg Controller.
+ * Read and verify the SNPSID register contents. The value should be
+ * 0x45f42xxx or 0x45f42xxx, which corresponds to either "OT2" or "OT3",
+ * as in "OTG version 2.xx" or "OTG version 3.xx".
+ */
+ if ((dwc2_get_gsnpsid(otg_dev->base) & 0xfffff000) != 0x4f542000 &&
+ (dwc2_get_gsnpsid(otg_dev->base) & 0xfffff000) != 0x4f543000) {
+ dev_err(&dev->dev, "Bad value for SNPSID: 0x%08x\n",
+ dwc2_get_gsnpsid(otg_dev->base));
+ retval = -ENODEV;
+ goto fail3;
+ }
+
+#ifndef DWC_HOST_ONLY
+ /* Initialize the PCD */
+ retval = dwc2_pcd_init(&dev->dev, otg_dev);
+ if (retval != 0) {
+ dev_err(&dev->dev, "dwc2_pcd_init failed\n");
+ otg_dev->pcd = NULL;
+ goto fail3;
+ }
+#endif
+
+ /* Set device flags indicating whether the HCD supports DMA */
+ if (dwc2_module_params.dma_enable > 0) {
+ pci_set_dma_mask(dev, DMA_BIT_MASK(32));
+ pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(32));
+ } else {
+ pci_set_dma_mask(dev, 0);
+ pci_set_consistent_dma_mask(dev, 0);
+ }
+
+ /* Initialize the HCD */
+ retval = dwc2_hcd_init(&dev->dev, otg_dev, dev->irq);
+
+ /*
+ * WARNING: dwc2_hcd_init() calls usb_create_hcd(), which overwrites
+ * the pci_dev drvdata, so we must set it again here
+ */
+ pci_set_drvdata(dev, otg_dev);
+
+ if (retval != 0) {
+ dev_err(&dev->dev, "dwc2_hcd_init failed\n");
+ otg_dev->hcd = NULL;
+ goto fail3;
+ }
+
+ /* Install the interrupt handler for the common interrupts */
+ dev_dbg(&dev->dev, "registering (common) handler for irq%d\n",
+ dev->irq);
+ retval = request_irq(dev->irq, common_irq,
+ IRQF_SHARED | IRQF_DISABLED | IRQ_LEVEL,
+ "dwc_otg", otg_dev);
+ if (retval) {
+ dev_err(&dev->dev, "request of irq%d failed\n", dev->irq);
+ retval = -EBUSY;
+ goto fail3;
+ } else {
+ otg_dev->common_irq_installed = 1;
+ }
+
+ dwc2_enable_global_interrupts(otg_dev->hcd);
+/*
+ dwc2_dump_global_registers(otg_dev->hcd);
+ dwc2_dump_host_registers(otg_dev->hcd);
+ dwc2_hcd_dump_state(otg_dev->hcd);
+*/
+ return 0;
+
+fail3:
+ dev_err(&dev->dev, "%s() FAILED, returning %d\n", __func__, retval);
+ driver_remove(dev);
+ return retval;
+
+fail2:
+ release_mem_region(otg_dev->rsrc_start, otg_dev->rsrc_len);
+fail1:
+ kfree(otg_dev);
+ return retval;
+}
+
+/*
+ * This structure defines the methods to be called by a bus driver
+ * during the lifecycle of a device on that bus. Both drivers and
+ * devices are registered with a bus driver. The bus driver matches
+ * devices to drivers based on information in the device and driver
+ * structures.
+ *
+ * The probe function is called when the bus driver matches a device
+ * to this driver. The remove function is called when a device is
+ * unregistered with the bus driver.
+ */
+static DEFINE_PCI_DEVICE_TABLE(pci_ids) = {
+ {
+ PCI_DEVICE(0x16c3, 0xabcd),
+ },
+ { /* end: all zeroes */ }
+};
+MODULE_DEVICE_TABLE(pci, pci_ids);
+
+/* pci driver glue; this is a "new style" PCI driver module */
+static struct pci_driver dwc2_driver = {
+ .name = "dwc_otg",
+ .id_table = pci_ids,
+
+ .probe = driver_probe,
+ .remove = driver_remove,
+
+ .driver = {
+ .name = driver_name,
+ },
+};
+
+/*
+ * dwc2_driver_init() - Called when the DWC_otg driver is installed (e.g. with
+ * the modprobe command). It registers the dwc2_driver structure with the
+ * appropriate bus driver. This will cause the dwc2_driver_probe function to
+ * be called. In addition, the bus driver will automatically expose attributes
+ * defined for the device and driver in the special sysfs file system.
+ */
+static int __init dwc2_driver_init(void)
+{
+ int retval;
+
+ pr_info("%s loaded\n", driver_name);
+
+ retval = pci_register_driver(&dwc2_driver);
+ if (retval)
+ pr_err("pci_register_driver() returned %d\n", retval);
+
+ return retval;
+}
+module_init(dwc2_driver_init);
+
+/*
+ * dwc2_driver_exit() - Called when the driver is removed (e.g. with the
+ * rmmod command). The driver unregisters itself with its bus driver.
+ */
+static void __exit dwc2_driver_exit(void)
+{
+ pci_unregister_driver(&dwc2_driver);
+
+ pr_info("%s removed\n", driver_name);
+}
+module_exit(dwc2_driver_exit);
+
+module_param_named(otg_cap, dwc2_module_params.otg_cap, int, 0444);
+MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP+SRP 1=SRP-only 2=None");
+
+module_param_named(dma_enable, dwc2_module_params.dma_enable, int, 0444);
+MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Disabled 1=Enabled");
+
+module_param_named(dma_desc_enable, dwc2_module_params.dma_desc_enable, int,
+ 0444);
+MODULE_PARM_DESC(dma_desc_enable, "Descriptor DMA Mode 0=Disabled 1=Enabled");
+
+module_param_named(dma_burst_size, dwc2_module_params.dma_burst_size, int,
+ 0444);
+MODULE_PARM_DESC(dma_burst_size,
+ "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256");
+
+module_param_named(speed, dwc2_module_params.speed, int, 0444);
+MODULE_PARM_DESC(speed, "Speed 0=High 1=Full");
+
+module_param_named(host_support_fs_ls_low_power,
+ dwc2_module_params.host_support_fs_ls_low_power, int,
+ 0444);
+MODULE_PARM_DESC(host_support_fs_ls_low_power,
+ "Support for Low Power w/FS or LS 0=Disabled 1=Enabled");
+
+module_param_named(host_ls_low_power_phy_clk,
+ dwc2_module_params.host_ls_low_power_phy_clk, int, 0444);
+MODULE_PARM_DESC(host_ls_low_power_phy_clk,
+ "Low Speed Low Power Clock 0=48Mhz 1=6Mhz");
+
+module_param_named(enable_dynamic_fifo,
+ dwc2_module_params.enable_dynamic_fifo, int, 0444);
+MODULE_PARM_DESC(enable_dynamic_fifo,
+ "Dynamic FIFO Sizing 0=Disabled 1=Enabled");
+
+module_param_named(host_rx_fifo_size, dwc2_module_params.host_rx_fifo_size,
+ int, 0444);
+MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in Rx FIFO 16-32768");
+
+module_param_named(host_nperio_tx_fifo_size,
+ dwc2_module_params.host_nperio_tx_fifo_size, int, 0444);
+MODULE_PARM_DESC(host_nperio_tx_fifo_size,
+ "Number of words in non-periodic Tx FIFO 16-32768");
+
+module_param_named(host_perio_tx_fifo_size,
+ dwc2_module_params.host_perio_tx_fifo_size, int, 0444);
+MODULE_PARM_DESC(host_perio_tx_fifo_size,
+ "Number of words in host periodic Tx FIFO 16-32768");
+
+module_param_named(max_transfer_size, dwc2_module_params.max_transfer_size,
+ int, 0444);
+/* Todo: Set the max to 512K, modify checks */
+MODULE_PARM_DESC(max_transfer_size,
+ "Maximum transfer size supported in bytes 2047-65535");
+
+module_param_named(max_packet_count, dwc2_module_params.max_packet_count,
+ int, 0444);
+MODULE_PARM_DESC(max_packet_count,
+ "Maximum number of packets in a transfer 15-511");
+
+module_param_named(host_channels, dwc2_module_params.host_channels, int,
+ 0444);
+MODULE_PARM_DESC(host_channels, "Number of host channels to use 1-16");
+
+module_param_named(phy_type, dwc2_module_params.phy_type, int, 0444);
+MODULE_PARM_DESC(phy_type, "Phy Type 0=Reserved 1=UTMI+ 2=ULPI");
+
+module_param_named(phy_utmi_width, dwc2_module_params.phy_utmi_width, int,
+ 0444);
+MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16
bits");
+
+module_param_named(phy_ulpi_ddr, dwc2_module_params.phy_ulpi_ddr, int, 0444);
+MODULE_PARM_DESC(phy_ulpi_ddr,
+ "ULPI at double or single data rate 0=Single 1=Double");
+
+module_param_named(phy_ulpi_ext_vbus, dwc2_module_params.phy_ulpi_ext_vbus,
+ int, 0444);
+MODULE_PARM_DESC(phy_ulpi_ext_vbus,
+ "ULPI PHY using internal or external VBus 0=Internal 1=External");
+
+module_param_named(i2c_enable, dwc2_module_params.i2c_enable, int, 0444);
+MODULE_PARM_DESC(i2c_enable, "FS PHY Interface (I2C) 0=No 1=Yes");
+
+module_param_named(ulpi_fs_ls, dwc2_module_params.ulpi_fs_ls, int, 0444);
+MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only 0=No 1=Yes");
+
+module_param_named(ts_dline, dwc2_module_params.ts_dline, int, 0444);
+MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs 0=No
1=Yes");
+
+module_param_named(en_multiple_tx_fifo,
+ dwc2_module_params.en_multiple_tx_fifo, int, 0444);
+MODULE_PARM_DESC(en_multiple_tx_fifo,
+ "Dedicated Non Periodic Tx FIFOs 0=Disabled 1=Enabled");
+
+module_param_named(lpm_enable, dwc2_module_params.lpm_enable, int, 0444);
+MODULE_PARM_DESC(lpm_enable, "LPM Support 0=Disabled 1=Enabled");
+
+module_param_named(ic_usb_cap, dwc2_module_params.ic_usb_cap, int, 0444);
+MODULE_PARM_DESC(ic_usb_cap, "IC_USB Capability 0=Disabled 1=Enabled");
+
+module_param_named(reload_ctl, dwc2_module_params.reload_ctl, int, 0444);
+MODULE_PARM_DESC(reload_ctl, "HFIR Reload Control 0=Disabled 1=Enabled");
+
+module_param_named(ahb_single, dwc2_module_params.ahb_single, int, 0444);
+MODULE_PARM_DESC(ahb_single, "AHB Single Support 0=Disabled 1=Enabled");
+
+module_param_named(otg_ver, dwc2_module_params.otg_ver, int, 0444);
+MODULE_PARM_DESC(otg_ver, "OTG revision supported 0=1.3 1=2.0");
+
+MODULE_DESCRIPTION("HS OTG USB Controller driver");
+MODULE_AUTHOR("Synopsys, Inc.");
+MODULE_LICENSE("GPL");
--
1.7.1
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