David and Paul:
Here's a question that doesn't seem to be answered in
Documentation/memory-barriers.txt. Are memory accesses within an
interrupt handler synchronized with respect to interrupts?
In more detail, suppose we have an interrupt handler that uses a memory
variable A. The device attached to the IRQ line sends two interrupt
requests, and we get:
CPU 0 CPU 1
----- -----
Receive IRQ
Call the interrupt handler
Write A
Finish IRQ processing
Receive IRQ
Call the interrupt handler
Read A
Finish IRQ processing
Is CPU 0's write to A guaranteed to be visible on CPU 1? Given that
interrupts on an IRQ line are serialized, and that IRQ processing must
involve some amount of memory barriers, I would expect the answer to be
Yes.
Does the answer change if the IRQ line is shared? I wouldn't expect
it to be.
Now, if the handler were bound to multiple IRQ (or MSI) lines, then
there'd be no reason to expect this to work. However, even in this
case, it seems that as long as we restrict our attention to handler
invocations in response to interrupt requests from one particular IRQ
line, the answer should be Yes. (For example, if device X on IRQ I and
device Y on IRQ J both used the same handler, a write to A in response
to an interrupt from device X should be visible the next time X sends
an interrupt.)
Do you know the answers?
Alan Stern
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