Hello. On 05/23/2014 10:39 PM, Paul Zimmerman wrote:
Newer DWC3 controllers can be built for USB 2.0-only mode, where most of the USB 3.0 circuitry is left out. To support this mode, the driver must limit the speed programmed into the DCFG register to Hi-Speed or lower.
Reads and writes to the PIPECTL register are left as-is, since they should be no-ops in USB 2.0-only mode. Calls to phy_init() etc. for the USB3 phy are also left as-is, since the no-op USB3 phy should be used for USB 2.0-only mode controllers.
Signed-off-by: Paul Zimmerman <[email protected]> --- Hi Felipe,
Does this look OK to you? I think it is fine to leave the PIPECTL accesses and the phy_init() calls as-is, but if you would prefer that I also conditionalize those I can do that. We have at least one customer who will need this feature fairly soon, so we would like to get this in without too much delay, although I guess we missed the 3.16 merge window.
-Paul
drivers/usb/dwc3/core.c | 7 +++++++ drivers/usb/dwc3/core.h | 13 +++++++++++++ 2 files changed, 20 insertions(+)
[...]
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 57332e3..48fb264 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -191,6 +191,19 @@ #define DWC3_GHWPARAMS1_PWROPT(n) ((n) << 24) #define DWC3_GHWPARAMS1_PWROPT_MASK DWC3_GHWPARAMS1_PWROPT(3) +/* Global HWPARAMS3 Register */ +#define DWC3_GHWPARAMS3_SSPHY_IFC(n) ((n) & 3) +#define DWC3_GHWPARAMS3_SSPHY_IFC_DIS 0 +#define DWC3_GHWPARAMS3_SSPHY_IFC_ENA 1 +#define DWC3_GHWPARAMS3_HSPHY_IFC(n) (((n) & (3 << 2)) >> 2)
Are you going to use this macro for the real register writes? It doesn't look right with that shifting to and fro.
+#define DWC3_GHWPARAMS3_HSPHY_IFC_DIS 0 +#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI 1 +#define DWC3_GHWPARAMS3_HSPHY_IFC_ULPI 2 +#define DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI 3 +#define DWC3_GHWPARAMS3_FSPHY_IFC(n) (((n) & (3 << 4)) >> 4)
Same question.
+#define DWC3_GHWPARAMS3_FSPHY_IFC_DIS 0 +#define DWC3_GHWPARAMS3_FSPHY_IFC_ENA 1 +
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