Add controller version based ULPI and UTMI phy initialization for
otg driver

Signed-off-by: Shengzhou Liu <shengzhou....@freescale.com>
Signed-off-by: Ramneek Mehresh <ramneek.mehr...@freescale.com>
Reviewed-by: Fleming Andrew-AFLEMING <aflem...@freescale.com>
Tested-by: Fleming Andrew-AFLEMING <aflem...@freescale.com>
---
 drivers/usb/phy/phy-fsl-usb.c | 20 ++++++++++++++++++++
 drivers/usb/phy/phy-fsl-usb.h |  7 +++++++
 2 files changed, 27 insertions(+)

diff --git a/drivers/usb/phy/phy-fsl-usb.c b/drivers/usb/phy/phy-fsl-usb.c
index 2b0f968..dcffeae 100644
--- a/drivers/usb/phy/phy-fsl-usb.c
+++ b/drivers/usb/phy/phy-fsl-usb.c
@@ -957,12 +957,32 @@ int usb_otg_start(struct platform_device *pdev)
        temp &= ~(PORTSC_PHY_TYPE_SEL | PORTSC_PTW);
        switch (pdata->phy_mode) {
        case FSL_USB2_PHY_ULPI:
+               if (pdata->controller_ver) {
+                       /* controller version 1.6 or above */
+                       setbits32(&p_otg->dr_mem_map->control,
+                               USB_CTRL_ULPI_PHY_CLK_SEL);
+                       /*
+                        * Due to controller issue of PHY_CLK_VALID in ULPI
+                        * mode, we set USB_CTRL_USB_EN before checking
+                        * PHY_CLK_VALID, otherwise PHY_CLK_VALID doesn't work.
+                        */
+                       clrsetbits_be32(&p_otg->dr_mem_map->control,
+                                USB_CTRL_UTMI_PHY_EN, USB_CTRL_IOENB);
+               }
                temp |= PORTSC_PTS_ULPI;
                break;
        case FSL_USB2_PHY_UTMI_WIDE:
                temp |= PORTSC_PTW_16BIT;
                /* fall through */
        case FSL_USB2_PHY_UTMI:
+               if (pdata->controller_ver) {
+                       /* controller version 1.6 or above */
+                       setbits32(&p_otg->dr_mem_map->control,
+                                USB_CTRL_UTMI_PHY_EN);
+                       /* Delay for UTMI PHY CLK to become stable - 10ms */
+                       mdelay(FSL_UTMI_PHY_DLY);
+               }
+               setbits32(&p_otg->dr_mem_map->control, USB_CTRL_UTMI_PHY_EN);
                temp |= PORTSC_PTS_UTMI;
                /* fall through */
        default:
diff --git a/drivers/usb/phy/phy-fsl-usb.h b/drivers/usb/phy/phy-fsl-usb.h
index 5986c96..653a4e8 100644
--- a/drivers/usb/phy/phy-fsl-usb.h
+++ b/drivers/usb/phy/phy-fsl-usb.h
@@ -199,6 +199,13 @@
 /* control Register Bit Masks */
 #define  USB_CTRL_IOENB                        (0x1<<2)
 #define  USB_CTRL_ULPI_INT0EN          (0x1<<0)
+#define  USB_CTRL_WU_INT_EN            (0x1<<1)
+#define  USB_CTRL_LINE_STATE_FILTER__EN        (0x1<<3)
+#define  USB_CTRL_KEEP_OTG_ON          (0x1<<4)
+#define  USB_CTRL_OTG_PORT             (0x1<<5)
+#define  USB_CTRL_PLL_RESET            (0x1<<8)
+#define  USB_CTRL_UTMI_PHY_EN          (0x1<<9)
+#define  USB_CTRL_ULPI_PHY_CLK_SEL     (0x1<<10)
 
 /* BCSR5 */
 #define BCSR5_INT_USB                  (0x02)
-- 
1.8.3.1

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