> From: dingu...@opensource.altera.com [mailto:dingu...@opensource.altera.com]
> Sent: Monday, September 15, 2014 8:23 AM
> 
> Hi Ming-Lei,
> 
> Thanks for your patch to enable the URB giveback in a tasklet context for
> the EHCI driver. I found your patch to fix a USB webcam timeout/stutter
> issue on the DWC2 HCD in the SOCFPGA platform.
> 
> However, I need your help trying to figure out why I need the 2nd patch to
> get your URB giveback patch to fully work.
> 
> I enable tracepoints in the dwc2 dwc2_handle_hcd_intr for 
> irq:irq_handler_entry
> and irq:irq_handler_exit. However, I did not see any measurable differences
> between enabling HCD_BH and no enabling HCD_BH. But I am able to get a full
> image from a webcam with the following 2 patches, and timeouts/green screen
> without the 2 patches.
> 
> I am using a Logitech HD C270 webcam.
> 
> Opening video decoder: [raw] RAW Uncompressed Video
> Movie-Aspect is undefined - no prescaling applied.
> VO: [sdl] 640x480 => 640x480 Packed YUY2
> Selected video codec: [rawyuy2] vfm: raw (RAW YUY2)
> 
> Can you provide any comments on the following issues:
> 
> 1) Am I placing the tracepoints in the right place for this non-ehci hcd?
> 2) I don't quite understand why removing local_irq_save/local_irq_restore
>    around the the complete makes the webcam work?
> 
> Thanks in advance for your comments.

Hi Dinh,

I'm not Ming, but I can hazard a guess why you are seeing this issue.

The webcam driver is likely doing a lot of processing in the ->complete
callback. With local interrupts disabled, this probably causes too long
of a delay in handling other interrupts. Since the SOCFPGA platform is
a uniprocessor (I think), there is no other CPU to handle the other
interrupts.

I think the only solution is to look at whatever driver is handling the
webcam, and see if it can re-enable interrupts earlier. I believe this
is an OK thing for it to do when the interrupt handler is threaded.

Ah, wait. I just looked at the specs, and I see the SOCFPGA is
dual-core. So the second core should be available for handling the
other interrupts. I wonder if something is wrong there? Is the 2nd CPU
actually running? Are interrupts getting disabled on both CPUs somehow?

-- 
Paul

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