Hi,
> The ohci-platform and ehci-platform drivers already perform their own
root-hub and bus resets.
I don't understand the sentence clearly.
Synopsis control VERSION： DesignWare Cores USB2.0 Host-AHB Controller, Version
2.98a
The synopsis has the three source clocks for EHCI Host Controller
implementation:
A, System (AHB BIU) Clock
B, PHY Clock(BUS clock)
C, UTMI PHY Clock(per port)
A clock corresponding to a reset, so the ehci control should have the same
number reset. We are ready to put the utmi phy clock and utmi reset into the
phy module. The ehci-platform is on the lack of a reset number.
Clock and reset detail:
Signal Description
ehci_hclk_i EHCI AHB System Clock
Function: The EHCI AHB System clock
supports 30- to 166- MHz
operation and has been tested at
40/50/60 MHz in FPGA technology. All
signal timings are related to the
rising edge of ehci_hclk_i. The EHCI
System Clock runs off this clock. For
correct synchronization between the
AHB and UTMI, the minimum required AHB
frequency is 30 MHz.
This clock is valid only if "Dedicated
AHB interface for EHCI and OHCI" is
Selected
ehci_hreset_i_n EHCI System Reset
Function: This active-low, synchronous
or asynchronous (depending on the
configuration) reset serves as power-on
reset and resets all the EHCI
control signals.
This signal is active only if
"Dedicated AHB interface for EHCI and OHCI" is
selected
Phy_clk_i Local EHCI PHY Clock
Function: This free-running clock
provides an operating frequency in the
Root Hub for clocking receive and
transmit parallel data.
phy_rst_i_n Power-on Reset
Function: This signal is synchronous
(asynchronous, if ASYNC reset option
selected) to phy_clk_i, and resets all
registers and state machines in receive
and transmit logic.
Best regards,
Pengcheng Li
> -----Original Message-----
> From: Alan Stern [mailto:[email protected]]
> Sent: Friday, March 18, 2016 1:52 AM
> To: Lipengcheng
> Cc: [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]
> Subject: Re: ehci and ohci reset number doubt
>
> On Thu, 17 Mar 2016, Lipengcheng wrote:
>
> > Hi,
> > In the files of ohci-platform.c and ehci-platform.c, they have only a
> > control reset. Can the files have one more controller reset?
>
> Currently only one reset is allowed.
>
> > Our usb2 controller using a synopsis, need bus reset, root hub reset,
> > utmi reset. The usb controller of reset and clock have the same
> number.
>
> If your platform has a Synopsis (now DesignWare) USB2 controller, why not use
> the dwc2 driver that's already in the kernel?
>
> The ohci-platform and ehci-platform drivers already perform their own
> root-hub and bus resets. They do not perform a UTMI reset, but they
> do call phy_init() and phy_power_on(). Will that be good enough for you?
>
> Alan Stern
