Hi,
On Fri, Jan 06, 2017 at 05:42:24PM -0600, Steven J. Hill wrote:
> Add all the necessary platform code to initialize the dwc3
> USB host controller found on OCTEON III processors. This
> code initializes the clocks and resets the USB core with
> PHYs. It is then passed off to the platform independent
> DWC3 driver found in the 'drivers/usb/dwc3' directory.
> Based off code written by David Daney.
>
> Signed-off-by: Steven J. Hill <[email protected]>
[...]
> +/* USB Control Register */
> +union cvm_usbdrd_uctl_ctl {
> + uint64_t u64;
> + struct cvm_usbdrd_uctl_ctl_s {
> + /* 1 = BIST and set all USB RAMs to 0x0, 0 = BIST */
> + __BITFIELD_FIELD(uint64_t clear_bist:1,
> + /* 1 = Start BIST and cleared by hardware */
> + __BITFIELD_FIELD(uint64_t start_bist:1,
> + /* Reference clock select for SuperSpeed and HighSpeed PLLs:
> + * 0x0 = Both PLLs use DLMC_REF_CLK0 for reference clock
> + * 0x1 = Both PLLs use DLMC_REF_CLK1 for reference clock
> + * 0x2 = SuperSpeed PLL uses DLMC_REF_CLK0 for reference clock &
> + * HighSpeed PLL uses PLL_REF_CLK for reference clck
> + * 0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock &
> + * HighSpeed PLL uses PLL_REF_CLK for reference clck
> + */
Maybe use kernel-doc comment style to document the fields?
> +typedef union cvm_usbdrd_uctl_ctl cvm_usbdrd_uctl_ctl_t;
[...]
> +typedef union cvm_usbdrd_uctl_host_cfg cvm_usbdrd_uctl_host_cfg_t;
[...]
> +typedef union cvm_usbdrd_uctl_shim_cfg cvm_usbdrd_uctl_shim_cfg_t;
These typedefs are not used, so they should not be added.
A.
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