On 12.10.2017 13:48, Hao Wei Tee wrote:
On 10/10/2017 22:13, Mathias Nyman wrote:
On 10.10.2017 12:41, David Laight wrote:
From: Robin Murphy
Sent: 09 October 2017 18:39
...
- without the IOMMU, block sizes >=128K all settle down into a
suspiciously-periodic error every 2048 sectors.
That stinks of being a problem where either the link TRB is part
way through a USB packet or where a buffer fragment crosses
a 64k boundary.
Neither is allowed.
Those should be taken care of by the xhci driver already
xhci_align_td() should make sure the link TRB is at packet boundary, and
TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) in xhci_queue_bulk_tx() should prevent
crossing 64k boundary in a TRB when queuing it.
more traces and logs of the VIA xhci controller could maybe tell something.
with the latest kernel:
echo 81920 > /sys/kernel/debug/tracing/buffer_size_kb
echo 1 > /sys/kernel/debug/tracing/events/xhci-hcd/enable
after failure:
cat /sys/kernel/debug/tracing/trace
Unfortunately since the failure on my VL805 is during xhci init tracing doesn't
produce anything we don't already know..
# tracer: nop
#
# _-----=> irqs-off
# / _----=> need-resched
# | / _---=> hardirq/softirq
# || / _--=> preempt-depth
# ||| / delay
# TASK-PID CPU# |||| TIMESTAMP FUNCTION
# | | | |||| | |
modprobe-964 [003] .... 240.271468: xhci_dbg_quirks: QUIRK:
Resetting on resume
modprobe-964 [003] .... 240.271471: xhci_dbg_init: // Halt the HC
modprobe-964 [003] .... 240.271477: xhci_dbg_init: // Reset the HC
And the associated DMA faults:
[ 265.286686] DMAR: DRHD: handling fault status reg 2
[ 265.286688] DMAR: [DMA Read] Request device [03:00.0] fault addr de28a000
[fault reason 01] Present bit in root entry is clear
I'll try and figure out exactly what de28a000 points at (or points after..).
Thanks.
You could try booting with xhci_hcd.dyndbg=+p added to the kernel command line.
It will show info about xHC registers when loading xhci, sample output:
[ 8.859865] xhci_hcd 0000:00:14.0: xHCI Host Controller
[ 8.865204] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus
number 1
[ 8.872718] xhci_hcd 0000:00:14.0: xHCI capability registers at
ffffc90001740000:
[ 8.880289] xhci_hcd 0000:00:14.0: CAPLENGTH AND HCIVERSION 0x1000080:
[ 8.886891] xhci_hcd 0000:00:14.0: CAPLENGTH: 0x80
[ 8.891747] xhci_hcd 0000:00:14.0: HCIVERSION: 0x100
[ 8.896783] xhci_hcd 0000:00:14.0: HCSPARAMS 1: 0x12000840
[ 8.902333] xhci_hcd 0000:00:14.0: Max device slots: 64
[ 8.907803] xhci_hcd 0000:00:14.0: Max interrupters: 8
[ 8.913182] xhci_hcd 0000:00:14.0: Max ports: 18
[ 8.918045] xhci_hcd 0000:00:14.0: HCSPARAMS 2: 0x14200054
[ 8.923602] xhci_hcd 0000:00:14.0: Isoc scheduling threshold: 4
[ 8.929774] xhci_hcd 0000:00:14.0: Maximum allowed segments in event ring:
5
[ 8.937085] xhci_hcd 0000:00:14.0: HCSPARAMS 3 0x200000a:
[ 8.942550] xhci_hcd 0000:00:14.0: Worst case U1 device exit latency: 10
[ 8.949510] xhci_hcd 0000:00:14.0: Worst case U2 device exit latency: 512
[ 8.956560] xhci_hcd 0000:00:14.0: HCC PARAMS 0x200077c1:
[ 8.962028] xhci_hcd 0000:00:14.0: HC generates 64 bit addresses
[ 8.968285] xhci_hcd 0000:00:14.0: HC hasn't Contiguous Frame ID Capability
[ 8.975501] xhci_hcd 0000:00:14.0: HC can generate Stopped - Short Package
event
[ 8.983161] xhci_hcd 0000:00:14.0: FIXME: more HCCPARAMS debugging
-Mathias
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