Hi Minas,
Am 07.12.2017 um 09:40 schrieb Stefan Wahren:
> Before flushing fifos required to check AHB master state and
> flush when AHB master is in IDLE state.
>
> Signed-off-by: Minas Harutyunyan <[email protected]>
> ---
> drivers/usb/dwc2/core.c | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/drivers/usb/dwc2/core.c b/drivers/usb/dwc2/core.c
> index dbca3b8890da..cbc7c562477f 100644
> --- a/drivers/usb/dwc2/core.c
> +++ b/drivers/usb/dwc2/core.c
> @@ -670,10 +670,23 @@ void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const
> int num)
>
> dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
>
> + /* Wait for AHB master IDLE state */
> + do {
> + udelay(1);
is this delay always necessary before reading GRSTCTL?
If yes please add a comment why.
If no please rework the loop in order to avoid this delay in case the
AHB master is already idle.
> + greset = dwc2_readl(hsotg->regs + GRSTCTL);
> + if (++count > 10000) {
> + dev_warn(hsotg->dev,
> + "%s() HANG! AHB Idle GRSTCTL=%0x\n",
> + __func__, greset);
> + return;
> + }
> + } while (!(greset & GRSTCTL_AHBIDLE));
> +
> greset = GRSTCTL_TXFFLSH;
> greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
> dwc2_writel(greset, hsotg->regs + GRSTCTL);
>
> + count = 0;
> do {
> greset = dwc2_readl(hsotg->regs + GRSTCTL);
> if (++count > 10000) {
> @@ -702,9 +715,23 @@ void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
>
> dev_vdbg(hsotg->dev, "%s()\n", __func__);
>
> + /* Wait for AHB master IDLE state */
> + do {
> + udelay(1);
> + greset = dwc2_readl(hsotg->regs + GRSTCTL);
> + if (++count > 10000) {
> + dev_warn(hsotg->dev,
> + "%s() HANG! AHB Idle GRSTCTL=%0x\n",
> + __func__, greset);
> + return;
> + }
> + } while (!(greset & GRSTCTL_AHBIDLE));
> +
> greset = GRSTCTL_RXFFLSH;
> dwc2_writel(greset, hsotg->regs + GRSTCTL);
>
> + /* Wait for RxFIFO flush done */
> + count = 0;
> do {
> greset = dwc2_readl(hsotg->regs + GRSTCTL);
> if (++count > 10000) {
--
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