On Wed, 2003-01-08 at 15:44, Stuart Biggerstaff wrote: > I think just a couple of things, and you've said this better than... > > At 03:14 PM 1/8/03 -0800, Aaron Grewell wrote: > >Well, let me see if I can get this right. L1 cache is always built into > >the processor. It's very fast but there isn't much of it, used to keep > >very frequently used information close at hand. L2 cache is usually > >built into modern processors. With the notable exception of the > >original Celeron it's been built in since the Pentium. > > Actually, wasn't it the Pentium Pro that introduced two levels of on-chip > cache to the x86? And it proved expensive for Intel to make, so the PII > included L2 within the packaging but not technically on the chip. > You're right about the PPro being the first, but I'm pretty sure it's now on-chip. I always viewed the packaging as mostly a shot at AMD, did it actually have another purpose?
> >With 386 and 486 > >processors L2 was optional, one of the features of a more expensive > >motherboard. > > Wasn't on-chip cache (along with the on-chip math co-processor--disabled in > SX models) the difference between the 386 and 486? > That's quite right, I had forgotten. No L1 in the 386 or lower. It was on-board. > >It's not as fast as L1, but is a lot bigger. Stuff that's > >used less often or is too big to fit in L1 will go into L2. L3 is > >unusual in the desktop market. The K6-III had it, but it's the only one > >I know of. > > K6-III only had L3 because it had an on-chip L2 but was designed for socket > 7 MBs that usually included L2--which became L3. > Ooh, I didn't forget that. I had no idea. > > It was what made that chip the last word in Socket 7 > >architecture, and also entirely too expensive for AMD to produce. Xeons > >and other high-end server chips (PA-RISC, SPARC, et al) > > And apparently G3-G4s. Yes, that's what you do when you can't scale your clock rates. > > >have it as > >well. It's only needed when lots of data is being thrown around, > >otherwise the extra cost isn't worth it. It is larger but slower than > >L2. Clever cache management is one of the features most important in a > >chip, and nowhere is that more clear than in a server chip that has 3 > >kinds to choose from and has to figure out where best to store its > >dataset. > > > > Stuart Biggerstaff > > Linda Hall Library of Science Engineering & Technology > 5109 Cherry St. > Kansas City, MO 64110 > > Phone: (816) 926-8748 > (800) 662-1545 x748 > FAX: (816) 926-8785 > URL: www.lindahall.org > > _______________________________________________ > Linux-users mailing list > [EMAIL PROTECTED] > Unsubscribe/Suspend/Etc -> http://www.linux-sxs.org/mailman/listinfo/linux-users _______________________________________________ Linux-users mailing list [EMAIL PROTECTED] Unsubscribe/Suspend/Etc -> http://www.linux-sxs.org/mailman/listinfo/linux-users
